K4D551638D SAMSUNG [Samsung semiconductor], K4D551638D Datasheet
K4D551638D
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K4D551638D Summary of contents
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... K4D551638D-TC 256Mbit GDDR SDRAM Samsung Electronics reserves the right to change products or specification without notice 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.8 October 2003 - 1 - 256M GDDR SDRAM Rev 1.8 (Oct. 2003) ...
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... Refresh cycle period of K4D551638D-TC50/60 is 8K/64ms. Revision 1.1 (March 21, 2003) • Changed VDD and VDDQ spec from 2.5V+5% to 2.6V+0.1V for all the frequency Revision 1.0 (February 27, 2003) • Changed the CAS Latency (CL) of K4D551638D-TC40 from • Defined DC spec. Revision 0.0 (January 16, 2003) - • Defined Target Specification ...
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... GENERAL DESCRIPTION FOR 4M x 16Bit x 4 Bank DDR SDRAM The K4D551638D is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized 4,194,304 words by 16 bits, fabricated with SAMSUNG extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications ...
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... K4D551638D-TC PIN CONFIGURATION PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use (Top View DDQ ...
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... K4D551638D-TC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF NC/RFU No connection/ Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK ...
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... K4D551638D-TC BLOCK DIAGRAM (4Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 4Mx16 4Mx16 4Mx16 4Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D551638D-TC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D551638D-TC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D551638D-TC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... IH DDQ 5. V (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate For any pin under test input of 0V < For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V. 8. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%. Symbol OUT V DD ...
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... CK and the input level The value expected to equal 0.5 For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V. 4. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5 Test Condition -2A Burst Lenth=2 tRC ≥ tRC(min) ...
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... CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition 1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V. 2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%. Output CAPACITANCE (V =2.6V Parameter Input capacitance( CK Input capacitance(A ~A ...
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... K4D551638D-TC AC CHARACTERISTICS Parameter Symbol CL=3 CK cycle time tCK CL=4 CK high level width tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in ...
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... K4D551638D-TC AC CHARACTERISTICS Parameter Symbol CL=3 CK cycle time tCK CL=4 CK high level width tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in ...
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... K4D551638D-TC Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming ...
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... K4D551638D-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 K4D551638D-TC45 Frequency Cas Latency 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 K4D551638D-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 K4D551638D-TC60 Frequency Cas Latency 166MHz ( 6 ...
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... K4D551638D-TC Simplified Timing @ BL CK, CK BA[1:0] BAa BAa Ra A10/AP Ra ADDR (A0~A9 A11,A12) WE DQS DQ Da0 Da1 Da2 Da3 DM COMMAND ACTIVEA WRITEA tRCD tRAS Normal Write Burst (@ BL= BAa BAa Ra Ra PRECH ACTIVEA tRP tRC tRRD Multi Bank Interleaving Write Burst ...
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... K4D551638D-TC PACKAGE DIMENSIONS (66pin TSOP-II) #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× 256M GDDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× Rev 1.8 (Oct. 2003) ...