AX88796LF ASIX Electronics, AX88796LF Datasheet - Page 38

• Manufacturer Part Number: AX88796LF
• Description: 3-in-1 Local CPU Bus Fast Rthernet Controller
• Manufacturer: ASIX Electronics

5.1.14 Test Register (TR) Offset 15H (Read)
5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)
5.1.16 GPO and Control (GPOC) Offset 17H (Write)
FIELD
FIELD
FIELD
7:4
3:1
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
0
AX88796 L
RST_10B 10BASE-T in Reset : This signal indicates that 10BASE-T logic of internal PHY is in reset.
RST_TX
PPDSET Internal PHY Power Down Setting:
AUTOD Autonegotiation Done : This signal goes high whenever internal PHY autonegotiation has
I_LINK This register reflects internal PHY link status value. Logic one means link ok.
MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.
MPSEL Media Priority Select :
NAME
NAME
NAME
RST_B Reset Busy : This signal indicates that internal PHY is in reset.
I_DPX This register reflects internal PHY duplex status value. Logic one means full duplex.
/GPO0 Default “0”. The register reflects to GPO[0] pin with inverted value.
I_SPD This register reflects internal PHY speed status value. Logic one means 100Mbps
GPI2
GPI1
GPI0
B
-
-
-
-
-
Reserved
100BASE-TX in Reset : This signal indicates that 100BASE-TX logic of internal PHY is
in reset.
completed. It will go low if autonegotiation has to restart.
Reserved
This register reflects GPI[2] input value. May connect to external PHY speed status.
This register reflects GPI[1] input value. May connect to external PHY duplex status.
This register reflects GPI[0] input value. May connect to external PHY link status.
Reserved
Reserved
Default “0”, Internal PHY is in normal operation mode
Write PPDSET to “1” force Internal PHY into power down mode
When MPSET is logic 0 , internal PHY is selected.
When MPSET is logic 1 , external MII PHY is selected.
MPSEL
Reserved
0
0
0
0
1
I_LINK
1
1
0
0
X
3-in-1 Local Bus Fast Ethernet Controller
GPI0
X
0
1
0
1
38
DESCRIPTION
DESCRIPTION
DESCRIPTION
Media Selected
Depend on MPSET bit
Internal PHY
Internal PHY
External MII PHY
Internal PHY
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