AX88796LF ASIX Electronics, AX88796LF Datasheet - Page 20

• Manufacturer Part Number: AX88796LF
• Description: 3-in-1 Local CPU Bus Fast Rthernet Controller
• Manufacturer: ASIX Electronics

If address Y is found to hash to the value 32 (20H), then FB32 in MAR2 should be initialized to ``1''. This will cause the
AX88796 to accept any multicast packet with the address Y.
Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64
logical address filteres if these addresses are chosen to map into unique locations in the multicast filter.
Note:
The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s, that is
the values are “FF FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the Protocol Control
Logic rejects the packet.
The final address filter decision depands on the destination address types, identified by the above 3 address
match filters, and the setup of parameters of Receive Configuration Register.
Definitions of address match filter result are as following:
The meaning of AB, AM and PRO signals, please refer to “
4.1.3 Broadcast Address Match Filter
4.1.4 Aggregate Address Filter with Receive Configuration Setup
The first bit of received packet sequence is 1’s stands by Multicast Address.
Signal
Phy
Mul
Bro
AGG
AX88796 L
Latch
1 of 64 bit decoder
Filter bit array
32-bit CRC Generator
X=31 to X=26
Value
=1
=0
=1
=0
=1
=0
=1
=0
Clock
Description
Unicast Address Match
Unicast Address not Match
Multicast Address Match
Multicast Address not Match
Brocast Address Match
Brocast Address not Match
Aggregate Address Match
Aggregate Address not Match
Selected bit
0 = reject, 1= accept
3-in-1 Local Bus Fast Ethernet Controller
20
Receive Configuration Register”
ASIX ELECTRONICS CORPORATION