AX88796LF ASIX Electronics, AX88796LF Datasheet - Page 35

• Manufacturer Part Number: AX88796LF
• Description: 3-in-1 Local CPU Bus Fast Rthernet Controller
• Manufacturer: ASIX Electronics

5.1.3 Interrupt mask register (IMR) Offset 0FH (Write)
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write)
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
FIELD
FIELD
6:2
4:3
2:1
7
6
5
4
3
2
1
0
7
1
0
7
6
5
0
AX88796 L
LB1,LB0 Encoded Loop-back Control
NAME
NAME
NAME
OVWE Overwrite Interrupt Enable. Default “low” disabled.
RDCR Remote DMA always completed
RDCE DMA Complete Interrupt Enable. Default “low” disabled.
CNTE
TXEE
RXEE
PRXE
PTXE
WTS
FDU
RLO
CRC
PD
-
-
-
-
Reserved
Counter Overflow Interrupt Enable. Default “low” disabled.
Transmit Error Interrupt Enable. Default “low” disabled.
Receive Error Interrupt Enable. Default “low” disabled.
Packet Transmitted Interrupt Enable. Default “low” disabled.
Packet Received Interrupt Enable. Default “low” disabled.
Reserved
Reserved
Word Transfer Select
Full Duplex :
Pad Disable
Retry of late collision
Reserved
Mode 0
Mode 1
Mode 2
Inhibit CRC
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
This bit indicates the current media mode is Full Duplex or not.
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
These encoded configuration bits set the type of loop-back that is to be performed.
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
0 : Half duplex
1 : Full duplex
LB1 LB0
0
1
0
0
1
0
3-in-1 Local Bus Fast Ethernet Controller
PHYcevisor loop-back
Normal operation
Internal AX88796 loop-back
35
DESCRIPTION
DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION