VT8601 Via, VT8601 Datasheet - Page 70

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Command List Operation
The ProMedia implements an internal block called the
“Command List Control Unit” to process command lists.
Command list operation is invisible to software.
initialization of the Command List Control Unit, software can
set registers as if there is no Command List Control Unit. If
an engine is idle and there are no pending commands in the
command buffer, data will be passed to the corresponding
register directly. Otherwise, address and data will be stored
into the command buffer to be processed later. When the
engine is idle, the Command List Control Unit will fetch
commands from the command buffer which is located in
video memory and send it to the engine.
registers that determine the lower and upper bounds of the
command buffer, the Command Buffer Start and Command
Buffer End registers. The Command List Control Unit uses
the command buffer in a round robin fashion, i.e., the address
is wrapped around when it passes the end of the buffer.
Registers in the Setup Engine, Rasterization Engine, Pixel
Engine, Memory Interface, and data from the host CPU and
the drawing environment can be buffered by the Command
List Control Unit. Command List Control registers and VGA
extension registers cannot be buffered. Every entry in the
command buffer is 64-bit with the lower 32 bits for the
register address and the higher 32 bits for register data. In
order to optimize memory bandwidth usage, the Command
List Control Unit maintains one read and one write FIFO in its
interface to memory in order to burst information from the
read/write command list.
Revision 1.3 September 8, 1999
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-64
Port 23B0 –Command Buffer Start Address .................. RW
Port 23B0 –Command Buffer End Address ................... RW
31-30 Command List Mode
29-24 Reserved
31-24 Reserved
23-0 Command Buffer Start Address
23-0 Command Buffer End Address
Starting address of the command buffer in bytes
(quadword aligned). Writing to this register will set
the internal buffer start and end pointers to this
address.
End address of the command buffer in bytes
(quadword aligned).
programmed to one more than the address of the last
byte of the command buffer.
00 Disable Command Buffer ...................... default
01 Enable Command Buffer
10 Flush Command Buffer Then Disable (after
11 -reserved-
Graphics Accelerator PCI Bus Master Registers
first completing any commands in the existing
command buffer)
........................................ always reads 0
........................................ always reads 0
VT8601 Apollo ProMedia
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