VT8601 Via, VT8601 Datasheet - Page 53

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Offset 78 - PMU Control 1 ................................ RW
Device 0 Offset 79 – PMU Control 2 ................................ RW
Revision 1.3 September 8, 1999
1-0
5
7
6
5
4
3
2
1
0
7
6
4
3
2
7HFKQRORJLHV ,QF
I/O Port 22 Access
Suspend Refresh Type
Reserved
Dynamic Clock Control
Reserved
AGPSTP# Control
Reserved
Memory Clock Enable (CKE) Function
CPU
Stopping
DRAM Controller Dynamic Clock Stopping
AGP Controller Dynamic Clock Stopping
PCI Interface Controller Dynamic Clock Stopping
Pseudo Power Good
South Bridge has High Priority
Reserved
:H &
:H &R R QQHFW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
CPU access to I/O address 22h is passed on to
the PCI bus .............................................default
CPU access to I/O address 22h is processed
internally
CBR Refresh ..........................................default
Self Refresh
Normal (clock is always running)...........default
Clock to various internal functional blocks is
disabled when those blocks are not being used
Disable ...................................................default
Enable
CKE Disable (pins used as MECC[2-0])..... def
CKE Enable (pins used for CKE[2-0]#)
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Interface
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
Controller
Dynamic
Clock
-47-
Device 0 Offset 7A – Miscellaneous Control .................. RW
Device 0 Offset 7E – PLL Test Mode .............................. RW
Device 0 Offset 7F – PLL Test Mode .............................. RW
6-4
2-1
7-6
5-0
7-0
7
3
0
No Time-Out Arbitration for Consecutive Frame
Accesses
Reserved
Background PCI-to-PCI Write Cycle Mode
Reserved
South Bridge PCI Master Force Timeout When
PCI Master Occupancy Timer Is Up
Reserved (status) ..................................................RO
Reserved (do not use) .................................default=0
Reserved (do not use) .................................default=0
0
1
0
1
0
1
Enable .................................................... default
Disable
Enable .................................................... default
Disable
Disable................................................... default
Enable
........................................ always reads 0
........................................ always reads 0
Device 0 Bus 0 Host Bridge Registers
VT8601 Apollo ProMedia