VT8601 Via, VT8601 Datasheet - Page 67

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Graphics Accelerator AGP Registers
The default base I/O address for the AGP registers is 2300h.
The AGP control unit has 3 channels. These channels can
work independently and in parallel. Each channel has its own
capabilities:
Channel 0: Execution mode texture access.
Channel 1: Command List Operation.
Channel 2: Data Move. Moves data from AGP memory to
Graphics AGP Configuration Registers
Port 2304 – Graphics AGP Capability List ..................... RW
Port 2334 – Graphics AGP Capability List Address ...... RW
Graphics AGP Operation Registers
Port 2340 – Graphics AGP FB Command List Start ..... RW
Port 2344 – Graphics AGP FB Command List Size ....... RW
Revision 1.3 September 8, 1999
31-19 Reserved
31-19 Reserved
31-0 xx
31-0 xx
18-0 Frame Buffer Command List Start Address
18-3 Frame Buffer Command List Size (in quadwords)
2-0
7HFKQRORJLHV ,QF
Value programmed is the desired size minus one
Reserved
:H &
:H &R R QQHFW
lists from AGP memory.
frame buffer or to the Capture/MPEG2 FIFO.
Also moves data from the frame buffer to AGP
memory.
QQHFW
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
Executes command
-61
Command List Format
The command list is stored in AGP memory in groups. Each
group has the following format:
The header is a 32-bit word that contains information about
this group, such as the amount of useful data in the group. A
group is always padded to a quadword boundary. Padding
DWORDs are discarded by the channel. The format of the
header is as follows:
QuadWord
29-8 Register Address of the First Data (ADDR)
15-0 Number of DWORDs of Data in this Group (LEN)
n / 2 + 1
31
30
…
0
1
2
Consecutive Addressing
Wait
0
1
0
1
Graphics Accelerator PCI Bus Master Registers
Disabled (all data in this group will be written
to the register with the destination address
specified in the “ADDR” field in bits 29-8)
Enabled (All data in this group will be written
to registers ADDR, ADDR+4, … ADDR+4 *
(LEN-1) sequentially
Don’t Wait (send data to the Graphics Engine
as long as it can receive it)
Wait (until the GE is idle, then send data)
63
Pad/Data n-1
VT8601 Apollo ProMedia
Data 0
Data 2
Data 4
Bit
48
…
32
31
Data n – 1/2
Header
Data 1
Data 3
Bit
…
16
0