HM17CM4096 ETC2 [List of Unclassifed Manufacturers], HM17CM4096 Datasheet - Page 13

• Manufacturer Part Number: HM17CM4096
• Description: 128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

PIN DESCRIPTION 2
D
D
12
WR (R/W)
8
,D
,D
RD (E)
SEL68
NAME
TEST
FLM
9
13
P/S
CS
RS
CL
FR
,D
,D
10
14
,D
,D
11
15
,
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
Chip selection pin.
Input data selection pin.
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
Test port.
Latching signal pin of display data.
LCD synchronous signal (first line marker) I/O pin.
Alternated display signal of LCD driver output I/O pin.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Connect to data bus to MPU with 8bit bi-directional bus.
Used as MSB 8bit data bus in the 16bit data RAM transfer mode
Set to “L” or “H” when not used.
Data in-out is possible when CS = “L”.
Distinguish bus data from CPU whether instruction or display
data.
RD signal connection port of 80 series CPU.
Data bus goes to output state at RD = “L”.
P/S
Enable signal connection port of 68 series CPU.
Active status when this signal is at “H”.
WR signal connection port of 80 series CPU.
Active at “L” and data bus signal is taken at the rising edge of
WR.
MPU.
CPU interface selection port
Serial / parallel interface selection port
H
Fix to ”L”.
Display line counter is counted up at the rising edge and LCD
driving signal is generated at the falling edge
Display start address is loaded in the display line counter at
FLM = “H”.
L
Read write control signal , R/W connection port of 68-series
class
P/S = “L” :serial interface selection ,D15~D5 goes to Hi-Z
select
state. Fix RD, WR to “H” or “L”.
chip
RS
CS
CS
SEL68
status
status
R/W
command
data/
RS
RS
instruction
68 series
H
FUNCTION
SDA(D
D
read
data
H
H
0
~D
7
1
)
RD, WR
write only
80 series
read/
write
display data
write
L
L
L
HM17CM4096
SCL (D
serial clock
-
0
)
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