MSP3411G Micronas, MSP3411G Datasheet - Page 84

• Manufacturer Part Number: MSP3411G
• Description: (MSP34x1G) Multistandard Sound Processor Family
• Manufacturer: Micronas

MSP 34x1G
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
Table 6–1: Demodulator Write Registers; Subaddress: 10
Table 6–2: Demodulator Read Registers; Subaddress: 11
84
Demodulator
Write Registers
AUTO_FM/AM
A2_Threshold
CM_Threshold
AD_CV
MODE_REG
FIR1
FIR2
DCO1_LO
DCO1_HI
DCO2_LO
DCO2_HI
PLL_CAPS
1)
Demodulator
Read Registers
C_AD_BITS
ADD_BITS
CIB_BITS
ERROR_RATE
PLL_CAPS
AGC_GAIN
not in BTSC, EIA-J, and FM-Radio mode
Address
(hex)
00 21
00 22
00 24
00 BB
00 83
00 01
00 05
00 93
00 9B
00 A3
00 AB
00 1F
Address
(hex)
00 23
00 38
00 3E
00 57
02 1F
02 1E
3451
all
3451
3451
MSP-
Version
3411,
all
all
3411,
MSP-
Version
3411,
1)
1)
Description
1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of
Automatic Switching between NICAM and FM/AM in case of bad NICAM
reception
2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic
Switching between NICAM and FM/AM in case of bad NICAM reception
A2 Stereo Identification Threshold
Carrier-Mute Threshold
SIF-input selection, configuration of AGC, and Carrier-Mute Function
Controlling of MSP-Demodulator and Interface options. As soon as this
register is applied, the MSP 34x1G works in the MSP 34x0D Compatibility
Mode.
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only
MSP 34x0D features are available; the use of MODUS and STATUS register
is not allowed.
The MSP 34x1G is reset to the normal mode by first programming the
MODUS register followed by transmitting a valid standard code to the
STANDARD SELECTION register.
FIR1-filter coefficients channel 1 (6 8 bit)
FIR2-filter coefficients channel 2 (6 8 bit),
Increment channel 1 Low Part
Increment channel 1 High Part
Increment channel 2 Low Part
Increment channel 2 High Part
Not of interest for the customer
Switchable PLL capacitors to tune open-loop frequency
Description
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits
NICAM: bit [10:3] of additional data bits
NICAM: CIB1 and CIB2 control bits
NICAM error rate, updated with 182 ms
Not for customer use
Not for customer use
hex
hex
; these registers are not readable!
; these registers are not writable!
3 8 bit offset (total 72 bit)
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
Reset
Mode
00 00
00 19
00 2A
00 00
00 00
00 00
00 00
00 56
hex
hex
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