XCB56364PV100 MOTOROLA [Motorola, Inc], XCB56364PV100 Datasheet - Page 30
XCB56364PV100
Manufacturer Part Number
XCB56364PV100
Description
24-Bit Audio Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.XCB56364PV100.pdf
(162 pages)
- Current page: 30 of 162
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No.
Specifications
Reset, Stop, Mode Select, and Interrupt Timing
2-10
26
27
28
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)
Interrupt Requests Rate
DMA Requests Rate
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is enabled
(OMR Bit 6 = 0)
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is not enabled
(OMR Bit 6 = 1)
• PLL is active during Stop (PCTL Bit 17 =
1) (implies no Stop delay)
• ESAI, SCI
• DMA
•
•
• Data read from ESAI, SCI
• Data write to ESAI, SCI
•
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
IRQ
IRQ
IRQ
,
,
,
NMI
NMI
NMI
Characteristics
(edge trigger)
(level trigger)
(edge trigger)
Freescale Semiconductor, Inc.
For More Information On This Product,
DSP56364 Advance Information
Go to: www.freescale.com
2, 3
PLC
PLC
ET
ET
PLC/2)
Expression
0.5)
C
5.5
C
12T
12T
8T
8T
6T
7T
3T
PDF + (128K
PDF + (20.5
C
C
C
C
C
C
C
T
T
C
C
T
C
6
(continued)
Min
13.6
12.3
55.0
—
—
—
—
—
—
—
MOTOROLA
120.0
120.0
Max
80.0
80.0
60.0
70.0
30.0
—
—
—
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
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