XCB56364PV100 MOTOROLA [Motorola, Inc], XCB56364PV100 Datasheet - Page 25
XCB56364PV100
Manufacturer Part Number
XCB56364PV100
Description
24-Bit Audio Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.XCB56364PV100.pdf
(162 pages)
- Current page: 25 of 162
- Download datasheet (3Mb)
2.6
MOTOROLA
Internal operation frequency
with PLL enabled
Internal operation frequency
with PLL disabled
Internal clock high period
Internal clock low period
Internal clock cycle time with
PLL enabled
Internal clock cycle time with
PLL disabled
Instruction cycle time
Notes:
• With PLL disabled
• With PLL enabled and
MF
• With PLL enabled and
MF > 4
• With PLL disabled
• With PLL enabled and
MF
• With PLL enabled and
MF > 4
Characteristics
INTERNAL CLOCKS
1.
2.
4
4
DF = Division Factor
Ef = External frequency
ET
MF = Multiplication Factor
PDF = Predivision Factor
T
See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion
of the PLL.
C
C
= internal clock cycle
= External clock cycle
Freescale Semiconductor, Inc.
For More Information On This Product,
DSP56364 Advance Information
Symbo
Table 2-4 Internal Clocks
I
T
T
T
Go to: www.freescale.com
T
CYC
l
f
f
H
C
C
L
PDF
PDF
PDF
PDF
0.49
0.47
0.49
0.47
Min
—
—
—
—
—
—
—
DF/MF
DF/MF
DF/MF
DF/MF
ET
ET
ET
ET
C
C
C
C
Expression
ET
(PDF
(Ef
2
C
DF/MF
Typ
Ef/2
ET
ET
T
—
—
—
—
C
PDF
MF)/
ET
C
C
DF)
C
1, 2
Internal Clocks
Specifications
PDF
PDF
PDF
PDF
0.51
0.53
0.51
0.53
Max
—
—
—
—
—
—
—
DF/MF
DF/MF
DF/MF
DF/MF
ET
ET
ET
ET
C
C
C
C
2-5
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