XCB56364PV100 MOTOROLA [Motorola, Inc], XCB56364PV100 Datasheet - Page 16
XCB56364PV100
Manufacturer Part Number
XCB56364PV100
Description
24-Bit Audio Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.XCB56364PV100.pdf
(162 pages)
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Signal/Connection Descriptions
Enhanced Serial Audio Interface
1-12
Signal
Name
SCKR
SCKT
FST
PC4
PC0
PC3
Input or output
Input or output
Input or output
disconnected
disconnected
disconnected
Input, output,
Input, output,
Input, output,
Signal Type
Table 1-10 Enhanced Serial Audio Interface Signals (continued)
or
or
or
Freescale Semiconductor, Inc.
State during
disconnected
disconnected
disconnected
disconnected
disconnected
disconnected
For More Information On This Product,
Reset
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DSP56364 Advance Information
Go to: www.freescale.com
Frame Sync for Transmitter—This is the transmitter frame sync
input/output signal. For synchronous mode, this signal is the frame
sync for both transmitters and receivers. For asynchronous mode,
FST is the frame sync for the transmitters only. The direction is
determined by the transmitter frame sync direction (TFSD) bit in the
ESAI transmit clock control register (TCCR).
Port C 4—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Receiver Serial Clock—SCKR provides the receiver serial bit clock
for the ESAI. The SCKR operates as a clock input or output used by
all the enabled receivers in the asynchronous mode (SYN=0), or as
serial flag 0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined
by the RCKD bit in the RCCR register. When configured as the output
flag OF0, this pin will reflect the value of the OF0 bit in the SAICR regis-
ter, and the data in the OF0 bit will show up at the pin synchronized to
the frame sync in normal mode or the slot in network mode. When con-
figured as the input flag IF0, the data value at the pin will be stored in
the IF0 bit in the SAISR register, synchronized by the frame sync in nor-
mal mode or the slot in network mode.
Port C 0—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Transmitter Serial Clock—This signal provides the serial bit rate
clock for the ESAI. SCKT is a clock input or output used by all
enabled transmitters and receivers in synchronous mode, or by all
enabled transmitters in asynchronous mode.
Port C 3—When the ESAI is configured as GPIO, this signal is indi-
vidually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Signal Description
MOTOROLA
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