H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 28

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H5TQ4G43AMR

Manufacturer Part Number
H5TQ4G43AMR
Description
4Gb DDR3 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
DDR3-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 29.
Rev. 1.0 / Dec. 2009
ACT to internal read or
command to first data
ACT to PRE command
CL = 10
PRE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
ACT to ACT or REF
command period
write delay time
Supported CWL Settings
Internal read
Parameter
Supported CL Settings
CL - nRCD - nRP
period
CWL = 6, 7
CWL = 5, 6
CWL = 5, 6
Speed Bin
CWL = 5
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 7
CWL = 7
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
t
t
t
t
t
RCD
RAS
AA
RP
RC
(13.125)
(13.125)
(13.125)
(49.125)
1.875
1.875
min
13.5
13.5
13.5
49.5
2.5
1.5
1.5
36
8
8
8
8
6, 8, (7), 9, (10)
DDR3-1333H
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5, 6, 7
9-9-9
9 * tREFI
<1.875
<1.875
< 2.5
< 2.5
max
3.3
20
Unit
n
n
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
1, 2, 3, 4, 6
1, 2, 3, 4, 6
1,2, 3,4, 6
1, 2, 3, 6
1, 2, 3, 4
1, 2, 3, 6
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
Note
4
4
4
4
4
4
28

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