H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 20

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H5TQ4G43AMR

Manufacturer Part Number
H5TQ4G43AMR
Description
4Gb DDR3 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
Table 5 - IDD2N and IDD3N Measurement-Loop Pattern
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.0 / Dec. 2009
0
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4-7
8-11
12-15
16-19
20-23
24-17
28-31
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
D
D
D
D
D
D
D
D
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a)
0
0
0
0
a)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
F
F
0
0
0
0
0
0
0
0
Data
Data
-
-
-
-
-
-
-
-
b)
b)
20

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