H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 17

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 / Dec. 2009
Symbol
I
I
DD6ET
DD6TC
I
DD7
Self-Refresh Current: Extended Temperature Range (optional)
T
ed
Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
MID_LEVEL
Auto Self-Refresh Current (optional)
T
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8
Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8
1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord-
ing to Table 10; Data IO: read data burst with different data between one burst and the next one
according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0,
1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Pattern Details: see Table 10.
CASE
CASE
e)
; CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8
: 0 - 95
: 0 - 95
o
o
C; Auto Self-Refresh (ASR): Disabled
C; Auto Self-Refresh (ASR): Enabled
f)
Description
b)
d)
d)
; ODT Signal: MID_LEVEL
;Self-Refresh Temperature Range (SRT): Normal
;Self-Refresh Temperature Range (SRT): Extend-
f)
a)
; AL: 0; CS, Command, Address,
a)
; AL: 0; CS, Command,
b)
; ODT Signal:
a), f)
; AL: CL-
b)
;
e)
17
;