DMA2275 MICRONAS [Micronas], DMA2275 Datasheet - Page 6

• Manufacturer Part Number: DMA2275
• Description: DMA 2275, DMA 2286 C/D/D2-MAC Descrambler
• Manufacturer: MICRONAS [Micronas]

DMA 2275, DMA 2286
3. Video Processor
The video processor consists of:
– Code Converter
– Video Descrambler
– Interpolation Filter
– Clamping and Video Gate
3.1. Code Converter
Input for the video processor is the digitized baseband
signal which may be delivered by the VCU 2133 in paral-
lel Gray code or by the UVC 3130 in simple binary code.
Therefore, a code converter from Gray to binary code is
intended. This converter can be disabled under software
control (bit 6 of video mode register) and can be
switched from 7 to 8 bit input (test bit TT6).
3.2. Video Descrambler
To make the transmitted video signal unintelligible, the
luma and/or chroma component are cut into two seg-
ments in the MAC encoder. These two segments are
then transposed. Task of the video descrambler is to re-
transpose the segments into their original waveform.
Three different video waveforms are possible:
– clear
– double–cut component rotation
– single–cut line rotation
The video descrambler has to cope with all these video
waveforms. In any case the output signal has a constant
delay of 1296 + 4 clock periods in order to avoid synchro-
nization problems during change of the video scram-
bling mode. For any video configurations not corre-
sponding to Fig. 3, part 2, p. 75 of ref. 1, the video
descrambler should be disabled by the software. The
signal is then passed through the descrambler unaf-
fected except for the delay of one line.
The baseband data burst signal passes the video des-
crambler through a special shift register, luma and chro-
ma rotation is done in within two video RAMs. The video
RAMs are subdivided into chroma and luma segments
which are organized as ringbuffer. The concerning ad-
dress counter is loaded every line with a start value de-
pending on the cut point (CPL or CPC) in case of scram-
bling, on the pan vector (PANV) in case of 16:9 aspect
ratio and in any case on an offset value which is pro-
grammable (FP register 33 and 34). The calculation of
the start address is done by the Fast Processor in real
time. The expansion of the compatible 4:3 part in case
of 16:9 aspect ratio is done by reading every third sam-
ple twice.
6
3.3. Interpolation Filter
If the compatible 4:3 part of a 16:9 picture is to be pro-
cessed (see Fig. 7, part 2, p. 79 of ref. 1), only this part
of the luma and chroma component is read out of the vid-
eo memory (262 chroma samples, 523 luma samples).
An interpolation filter is then used to regain the number
of samples expected by the DMA 2271 or DMA 2281
(349 chroma samples, 697 luma samples). The sam-
pling rate ratio is 4:3. The filter function is defined by a
set of 16 coefficients, which are programmable. Down-
load of these coefficients into the interpolation filter is a
one shot function triggered by software (bit 4 of vid-
eo_mode register).
The interpolation is not influenced by the video scram-
bling method, because the output signal of the video
memory appears unscrambled. The position of the com-
patible 4:3 part is programmable so that user panning is
possible. The panning can also be controlled by the
broadcaster when sending real time pan vectors in line
625. The selection of these two panning modes is done
by bit 7 of the scram_mode registers.
The high frequency losses in the interpolation filter can
be partly compensated with a peaking filter. Low peaking
increases the signal level about 6 dB at 5 MHz, high
peaking increases the signal level about 10 dB at 5 MHz.
Peaking is controlled with bit 0 and 1 in the video_mode
register.
Alternatively the interpolation and peaking filter can be
used for baseband filtering. It is then enabled not only
during active video, but also during the data burst and
VBI transmission. The filter coefficients have to be
changed for this application.
3.4. Clamping and Video Gate
The DC level of the analog baseband signal is controlled
by the clamping circuit of the DMA 2271 or DMA 2281
decoder chip which measures the clamping period of
each line. The line store in the video descrambler of the
DMA 2275 or DMA 2286 would cause a line delay within
the clamping control loop with all corresponding prob-
lems.
Therefore, the line store of the descrambler chip is by-
passed during the clamping period to avoid the line
delay. The position of the clamping bypass within the line
can be programmed in steps of 99 clock cycles (bit 3–0
in mac_mode register). Clamp position ‘0’ would be lo-
cated after the first subframe of a D–MAC signal. Clamp
position ‘1’ is the default specified in ref 1. The clamp by-
pass is automatically disabled in line 625 and line 1.
Finally, a video gate is provided to switch the luminance
component to black and the chrominance component to
zero in case of denied access to the video service. This
gate can be used in country by country control (CbCC)
applications to black out special programs under soft-
ware control (bit 5 of video_mode register).