DMA2275 MICRONAS [Micronas], DMA2275 Datasheet - Page 16

• Manufacturer Part Number: DMA2275
• Description: DMA 2275, DMA 2286 C/D/D2-MAC Descrambler
• Manufacturer: MICRONAS [Micronas]

DMA 2275, DMA 2286
Table 8–3: IM Bus register of the DMA 2286
16
Address
203
194
195
196
197
198
204
Label
C1A
C1E
C1U
C1M
see register 203
see register 203
see register 203
SFS
CD
AUM
DRS
CS
SBE
DGT
P0R
P0C
DSB
Bit No.
0–9
10
11
12–15
0–10
13
14
15
14, 15
0–3
4–7
8
9
10
Function
channel 1 packet address
channel 1 packet selection enable
channel 1 mode update
channel 1 mode
channel 2
channel 3
channel 4
subframe select
SFS = sample number of the first bit in the selected subframe
examples:
DRS = 1,
DRS = 1,
DRS = 0,
chip definition
0 = DMA 2271/2281
1 = DMA 2286
auto mode
0 = auto mode off
1 = sound coding in packet header
data rate select
0 = 10.125 Mb/s
1 = 20.25 Mb/s
chip select
0 = imbus of DMA 2271/2281 active
1 = imbus of DMA 2286 active
s_bus enable, each bit enables one s_bus channel
data group type selection
packet 0 reset
1: select first byte in packet 0 buffer (first byte = data group type DGT)
packet 0 clear
1: enable packet 0 buffer to store next packet 0
disable s_bus data output (pin 66)
0 = enabled
1 = high impedance
linear/nicam
hamming/parity protection
high/medium quality
stereo/mono
channel 1 enable
channel 2 enable
channel 3 enable
channel 4 enable
first subframe
second subframe SFS = 106
first subframe
D2 MAC
C/D MAC
SFS = 7
SFS = 14
undelayed packet output of sound proc.
packet output delayed by 128 s