MA100H MEGAWIN [Megawin Technology Co., Ltd], MA100H Datasheet - Page 4

• Manufacturer Part Number: MA100H
• Description: UART-to- USB Bridge Controller
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

Application Notice
1. Time-out between RX and USB:
2. TX/RX-pin is an open-drain pin:
The TX/RX is an open-drain circuit, So, It decide that how much the suspend current, That is,
If the power of device A is more than 4.0V, The VCC_UART’s power must be connect to the power
of device A, Otherwise, The VCC_UART’s power should be connect to V3.3 pin of the MA100
3. UART’s TX data delay
There is a time gap between the bytes transmitted via MA100’s TX-pin. When the frequency of
oscillator is 6 MHz, the minimum time gap is 10 microseconds. Users need to make sure the UART
receiver device could move the data from the receiving buffer during the time gap, 10 us, to avoid it
being overwritten by the following byte of data. The signal timing is shown in the following.
Megawin MA100 Application Circuit
Time-out = 1/baud rate x 2
4
R1 and R2 must be connected to VCC_UART which is the power of device A.
If the power of device A is more than 4.0V,
Otherwise, VCC_UART should be 3.3V applied by MA100.
Device A
VBus
GND
U2
D+
D-
C6
C7
30P
30P
RX
TX
VDD
R3 30
R4 30
VCC_UART
XTAL1
XTAL2
6MHZ
R1
4.7k
D-
D+
R2
4.7k
VCC_UART
n
C5
1u
TX
RX
, where n=0 for TO1=1 and TO0=1, n=1 for TO1=1 and TO0=0;
C3
15P
n=2 for TO1=0 and TO0=1, n=3 for TO1=0 and TO0=0.
MA100 Data Sheet
XTAL1
XTAL2
TX
RX
V3.3
D-
10
11
12
13
14
1
2
3
4
5
6
7
8
9
V3.3
D-
Vss
XTAL1
XTAL2
NC
TX
RX
LBRS
P0
EE_A0
EE_A1
EE_SCL
EE_SDA
U1
USB_LED
MA100L
RX_LED
TX_LED
-RST
BS2
BS1
BS0
TO1
TO0
Vcc
NC
NC
NC
D+
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D+
USB_LED
RX_LED
TX_LED
Title
Size
Date:
C8
0.1u
A
Megawin Technology Inc.
C4
15P
Document Number
Megawin MA100 Application Circuit
Optional
Friday, May 19, 2006
C2
0.1u
EE_A0
EE_A1
GND
GND
VDD
C1
10u
1
2
3
4
A0
A1
A2
GND
U3
AT24C08
VCC
SDA
SCL
WP
USB_LED
RX_LED
TX_LED
5
6
7
8
Sheet
VDD
GND
EE_SCL
EE_SDA
LED
LED
LED
MEGAWIN
D1
D2
D3
VDD
1
of
1
Rev
1.1