8S89874BKILF IDT [Integrated Device Technology], 8S89874BKILF Datasheet - Page 11

• Manufacturer Part Number: 8S89874BKILF
• Description: 1:2 Differential-to-LVPECL Buffer/Divider
• Manufacturer: IDT [Integrated Device Technology]

ICS8S89874I Data Sheet
ICS8S89874BKI REVISION A OCTOBER 22, 2010
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins has internal pullups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 4A. 3.3V LVPECL Output Termination
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
11
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4B. 3.3V LVPECL Output Termination
3.3V
LVPECL
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
©2010 Integrated Device Technology, Inc.
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input