PPC440EPX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440EPX-NPAFFFTS Datasheet - Page 61

• Manufacturer Part Number: PPC440EPX-NPAFFFTS
• Description: PowerPC 440EPx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 1.26 – October 15, 2007
Table 8. Signal Functional Description (Sheet 5 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3 kΩ to OV
3. Must pull down (recommended value is 1 kΩ)
4. If not used, must pull up (recommended value is 3 kΩ to OV
5. If not used, must pull down (recommended value is 1 kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
Preliminary Data Sheet
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldReq
HoldPri
PerClk
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin, where n = 0
2. Two 4-pin, where n = 0 & 1
3. One 4-pin, where n = 0 and two 2-pin, where n = 1 & 2
4. Four 2-pin, where n = 0 & 1 & 2 & 3
UARTSerClk
UARTn_Rx
UARTn_Tx
UARTn_DCD
UARTn_DSR
UARTn_CTS
UARTn_DTR
UARTn_RTS
UARTn_RI
IIC Peripheral Interface
IIC0SClk
IIC0SData
IIC1SClk
IIC1SData
Signal Name
Bus Request. Used when the PPC440EPx needs to regain
control of peripheral interface from an external master.
External Acknowledgement. Used by the PPC440EPx to indicate
that a data transfer occurred.
External Request. Used by an external master to indicate it is
prepared to transfer data.
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
Note: The state of signals or clocks cannot be guaranteed until
the ExtReset signal has been de-asserted.
Hold Acknowledge. Used by the PPC440EPx to transfer
ownership of peripheral bus to an external master.
Hold Request. Used by an external master to request ownership
of the peripheral bus.
Hold Primary. Used by an external master to indicate the priority
of a given external master tenure.
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
The SerClk input provides an alternative to the internally
generated serial clock. It is used in cases where the allowable
internally generated clock rates are not satisfactory.
Receive data.
Transmit data.
Data Carrier Detect.
Data Set Ready.
Clear To Send.
Data Terminal Ready.
Request To Send.
Ring Indicator.
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
DD
(EOV
Description
DD
DD
for Ethernet)
440EPx – PPC440EPx Embedded Processor
(EOV
DD
for Ethernet)
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-up
Type
Rcvr
Notes
1, 4
1, 4
1, 6
1, 6
1, 6
1, 2
1, 2
1
1
1
1
1
1
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