GS881Z18T GSI [GSI Technology], GS881Z18T Datasheet - Page 8

• Manufacturer Part Number: GS881Z18T
• Description: 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
• Manufacturer: GSI [GSI Technology]

Synchronous Truth Table
Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The address counter is incriminated for all Burst continue cycles.
Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.
G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
Operation
Type Address E
W
W
D
D
D
D
R
R
B
B
B
B
External
External
External
Current
None
None
None
None
None
None
Next
Next
Next
Next
H
X
X
X
X
X
X
X
X
X
L
L
L
L
1
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E
X
X
X
H
X
H
X
H
X
H
X
X
X
L
2
E
H
X
X
X
X
X
X
X
X
X
L
L
L
L
3
ZZ ADV W Bx G CKE CK
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
L
X
L
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
L
L
GS881Z18/36T-11/100/80/66
H
H
X
X
X
X
L
L
X
X
X
X
X
X
© 1998, Giga Semiconductor, Inc.
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Preliminary
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z 1,2,3,10
High-Z
DQ
Q
Q
D
D
-
Notes
1,2,10
1,3,10
1,10
2,3
1
2
3
4
.