GS881Z18T GSI [GSI Technology], GS881Z18T Datasheet - Page 26

• Manufacturer Part Number: GS881Z18T
• Description: 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
• Manufacturer: GSI [GSI Technology]

(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-
compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
SAMPLE/PRELOAD
Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
1
0
Test Logic Reset
Run Test Idle
0
1
1
1
26/34
Capture DR
1
Update DR
Pause DR
Select DR
Exit1 DR
Shift DR
Exit2 DR
0
0
1
1
0
1
0
1
0
0
0
1
1
Capture IR
Update IR
1
Pause IR
Select IR
GS881Z18/36T-11/100/80/66
Exit1 IR
Shift IR
Exit2 IR
0
1
1
© 1998, Giga Semiconductor, Inc.
0
1
0
0
1
0
0
0
Preliminary
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