GS8662S08E GSI [GSI Technology], GS8662S08E Datasheet
GS8662S08E
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GS8662S08E Summary of contents
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... GS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. ...
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... NW0 controls writes to D0:D3. NW1 controls writes to D4:D7 recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 SigmaQuad SRAM—Top View R/W NW1 ...
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... Notes controls writes to D0: recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 SigmaQuad SRAM—Top View R ...
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... BW0 controls writes to D0:D8. BW1 controls writes to D9:D17 recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 SigmaQuad SRAM—Top View R/W BW1 ...
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... BW2 controls writes to D18:D26. BW3 controls writes to D27:D35 recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 SigmaQuad SRAM—Top View R/W BW2 ...
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Pin Description Table Symbol SA Synchronous Address Inputs NC R/W NW0–NW1 BW0–BW1 BW0–BW3 K C TMS TDI TCK TDO V HSTL Input Reference Voltage REF ZQ Output Impedance Matching Input OFF ...
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... SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired. Each of the three SigmaQuad Family SRAMs— ...
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... Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered- specific sequence in order to avoid undefined operations. Power-Up Sequence 1. Power-up and maintain Doff at low state. 1a. Apply 1b. Apply V . DDQ 1c. Apply V (may also be applied at the same time as V REF 2. After power is achieved and clocks ( are stablized, change Doff to high. ...
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... Unchanged Output Register Control SigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks ...
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Example Four Bank Depth Expansion Schematic – – Bank ...
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... CQ Bank 1 CQ Bank 1 C Bank 2 C Bank 2 Q Bank 2 CQ Bank 2 CQ Bank 2 Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 Burst of 2 SigmaSIO-II SRAM Depth Expansion Write D Read E Write B+1 D+1 D ...
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... HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range guarantee impedance matching with a vendor-specified tolerance is between 150Ω ...
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Byte Write Clock Truth Table ↑ ↑ n+1 n Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t ...
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Byte Write Enable (BWn) Truth Table BW3 BW2 BW1 BW0 ...
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LOAD LOAD READ DDR Read Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 State Diagram Power-Up LOAD NOP LOAD Load New WRITE DDR Write 15/37 Preliminary LOAD LOAD © 2005, GSI ...
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Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ V Voltage in V REF V Voltage on I/O Pins I/O V Voltage on Other Input Pins IN ...
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HSTL I/O DC Input Characteristics Parameter DC Input Logic High DC Input Logic Low Note: Compatible with both 1.8 V and 1.5 V I/O drivers HSTL I/O AC Input Characteristics Parameter AC Input Logic High AC Input Logic Low V ...
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Capacitance 3 Parameter Input Capacitance Output Capacitance Note: This parameter is sample tested. AC Test Conditions Parameter Input high level Input low level Max. ...
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Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Notes /2) / (RQ/5) +/– 15 DDQ /2) ...
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Operating Currents Parameter Symbol I Operating Current (x36): DDR DD I Operating Current (x18): DDR DD I Operating Current (x9): DDR DD I Operating Current (x8): DDR DD I Standby Current (NOP): DDR SB1 All Inputs Notes: 1. Power measured ...
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AC Electrical Characteristics Parameter Symbol Clock K, K Clock Cycle Time C, C Clock Cycle Time tTKC Variable K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low ...
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... To avoid bus contention given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten- tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V not possible for two SRAMs on the same board such different voltages and tempera- tures. ...
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K Controlled Read-First Timing Diagram Read A KHKL KHKL KHKH KHKH KLKH KLKH K K AVKH KHAX Address A IVKH LD IVKH R/W BWx Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For ...
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K Controlled Write-First Timing Diagram NOP K K Address IVKH LD R/W BWx D Q KHCQX KHCQV CQ CQ Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 Write A Read B ...
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C Controlled Read-First Timing Diagra Read A KHKL KHKL KHKH KHKH KLKH KLKH K K AVKH KHAX Address A IVKH KHIX LD R/W BWx D KHCH CHCL CHCL Rev: 1.01 9/2005 Specifications cited are subject ...
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C Controlled Write-First Timing Diagram NOP K K Addr IVKH LD R/W BWx JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE ...
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JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS input is sampled ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. ...
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TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR ...
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... Input Low Voltage Output High Voltage (I OH Output Low Voltage (I OL Note: The input level of SRAM pin is to follow the SRAM DC specification. Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 Description Symbol ...
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... Input and Output Timing Reference Level Notes: 1. Distributed scope and test jig capacitance. 2. Test conditions as shown unless otherwise noted. TCK TDI TMS TDO Parallel SRAM input Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 Symbol TR/TF ...
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... TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662S08/09/18/36E-333/300/250/200/167 Symbol Min ...
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Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.01 ...
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... Ordering Information—GSI SigmaSIO-II SRAM 1 Org Part Number GS8662S36E-333 GS8662S36E-300 GS8662S36E-250 GS8662S36E-200 GS8662S36E-167 GS8662S36E-333I GS8662S36E-300I GS8662S36E-250I GS8662S36E-200I GS8662S36E-167I GS8662S18E-333 GS8662S18E-300 GS8662S18E-250 GS8662S18E-200 GS8662S18E-167 GS8662S18E-333I ...
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... Ordering Information—GSI SigmaSIO-II SRAM 1 Org Part Number GS8662S09E-167I GS8662S08E-333 GS8662S08E-300 GS8662S08E-250 GS8662S08E-200 GS8662S08E-167 GS8662S08E-333I GS8662S08E-300I GS8662S08E-250I GS8662S08E-200I GS8662S08E-167I GS8662S36GE-333 GS8662S36GE-300 GS8662S36GE-250 GS8662S36GE-200 GS8662S36GE-167 GS8662S36GE-333I ...
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... Ordering Information—GSI SigmaSIO-II SRAM 1 Org Part Number GS8662S18GE-167I GS8662S09GE-333 GS8662S09GE-300 GS8662S09GE-250 GS8662S09GE-200 GS8662S09GE-167 GS8662S09GE-333I GS8662S09GE-300I GS8662S09GE-250I GS8662S09GE-200I GS8662S09GE-167I GS8662S08GE-333 GS8662S08GE-300 GS8662S08GE-250 GS8662S08GE-200 GS8662S08GE-167 ...