GS8662Q08E GSI [GSI Technology], GS8662Q08E Datasheet - Page 13

• Manufacturer Part Number: GS8662Q08E
• Description: 72Mb SigmaQuad-II Burst of 2 SRAM
• Manufacturer: GSI [GSI Technology]

FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
SigmaQuad-II B2 Coherency and Pass Through Functions
Because the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what
constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately
after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the
same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the
SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
SS
Dwg Rev. G
Address
/BWx
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
/W
/K
/R
/C
K
D
C
Q
DB0
Read
5
OO
A
DB1
Write
6
OI
B
SigmaQuad-II B2 Coherency and Pass Through Functions
DD0
Read
8
C
OI
DD1
Write
2
OO
D
13/35
QA0
?
DF0
Read
7
OO
E
COHERENT
QA1
?
DF1
Write
1
OO
GS8662Q08/09/18/36E-300/250/200/167
F
QC0
5
DH0
Read
9
OI
G
PASS-THRU
QC1
6
DH1
Write
3
IO
H
© 2005, GSI Technology
QE0
7
Preliminary
DI0
4
OO
I
QE1
1