GS8662Q08E GSI [GSI Technology], GS8662Q08E Datasheet
GS8662Q08E
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GS8662Q08E Summary of contents
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... SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are synchronous devices ...
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... BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 2. MCL = Must Connect Low Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 SigmaQuad-II SRAM—Top View BW2 ...
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... TDO TCK SA Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. MCL = Must Connect Low Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 SigmaQuad-II SRAM—Top View BW1 ...
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... TDO TCK SA Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. MCL = Must Connect Low Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 SigmaQuad-II SRAM—Top View NW1 ...
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... TDO TCK SA Note: MCL = Must Connect Low Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 SigmaQuad-II SRAM — Top View ...
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Pin Description Table Symbol SA Synchronous Address Inputs BW0–BW3 NW0–NW1 TMS TDI TCK TDO V HSTL Input Reference Voltage REF ZQ Output Impedance Matching Input Qn Synchronous Data Outputs Dn D off ...
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... Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’ ...
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... K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle. SigmaQuad-II B2 Double Data Rate SRAM Write First Write A ...
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... Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered- specific sequence in order to avoid undefined operations. Power-Up Sequence 1. Power-up and maintain Doff at low state. 1a. Apply 1b. Apply V . DDQ 1c. Apply V (may also be applied at the same time as V REF 2. After power is achieved and clocks ( are stablized, change Doff to high. ...
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... Beat 1 Output Register Control SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks ...
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Example Four Bank Depth Expansion Schematic – – Bank ...
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Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 12/35 Preliminary © 2005, GSI Technology ...
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... HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must the value of the desired RAM output impedance. The allowable range guarantee impedance matching continuously is between 150Ω ...
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... Notes Don’t Care High Low Valid evaluated on the rising edge and Q1 are the first and second data output transfers in a read. Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table A W BWn BWn K ↑ K ↑ K ↑ ...
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Byte Write Enable (BWn) Truth Table BW0 BW1 BW2 BW3 Don’t Care Don’t Care Don’t Care ...
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Read NOP READ READ Load New Read Address Always (Fixed) DDR Read Notes: 1. Internal burst counter is fixed as 1-bit linear (i.e., when first address is A0+), next internal burst address is A0+1. 2. “READ” refers to read active ...
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Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ V Voltage in V REF V Voltage on I/O Pins I/O V Voltage on Other Input Pins IN ...
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HSTL I/O DC Input Characteristics Parameter DC Input Logic High DC Input Logic Low Notes: 1. Compatible with both 1.8 V and 1.5 V I/O drivers 2. These are DC test criteria. DC design criteria is V eters. (Min)AC = ...
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Capacitance 1 Parameter Input Capacitance Output Capacitance Clock Capacitance Note: This parameter is sample tested. AC Test Conditions Parameter Input high level Input low ...
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Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Notes /2) / (RQ/5) +/– 15 DDQ /2) ...
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AC Electrical Characteristics Parameter Clock K, K Clock Cycle Time C, C Clock Cycle Time tKC Variable K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low Pulse ...
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... To avoid bus contention given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V not possible for two SRAMs on the same board such different voltages and temperatures. 5. ...
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Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 23/35 Preliminary © 2005, GSI Technology ...
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Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 24/35 Preliminary © 2005, GSI Technology ...
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JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale ...
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Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels ...
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ID Register Contents Bit # x36 ...
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Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
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EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal ...
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... Input High Voltage Input Low Voltage Output High Voltage (I OH Output Low Voltage (I OL Note: The input level of SRAM pin is to follow the SRAM DC specification. JTAG Port AC Test Conditions Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Notes: 1 ...
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... TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Rev: 1.01 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662Q08/09/18/36E-300/250/200/167 ...
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Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.01 ...
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... GS8662Q09E-167I GS8662Q08E-300 GS8662Q08E-250 GS8662Q08E-200 GS8662Q08E-167 GS8662Q08E-300I GS8662Q08E-250I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662x36E-200T Commercial Temperature Range Rev: 1.01 9/2005 Specifications cited are subject to change without notice ...
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... Ordering Information—GSI SigmaQuad-II SRAM 1 Org Part Number GS8662Q08E-200I GS8662Q08E-167I GS8662Q36GE-300 GS8662Q36GE-250 GS8662Q36GE-200 GS8662Q36GE-167 GS8662Q36GE-300I GS8662Q36GE-250I GS8662Q36GE-200I GS8662Q36GE-167I GS8662Q18GE-300 GS8662Q18GE-250 GS8662Q18GE-200 GS8662Q18GE-167 GS8662Q18GE-300I GS8662Q18GE-250I ...
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... Ordering Information—GSI SigmaQuad-II SRAM 1 Org Part Number GS8662Q08GE-300I GS8662Q08GE-250I GS8662Q08GE-200I GS8662Q08GE-167I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662x36E-200T Commercial Temperature Range Rev: 1.01 9/2005 Specifications cited are subject to change without notice ...