GS880E32T-100 GSI [GSI Technology], GS880E32T-100 Datasheet - Page 19
GS880E32T-100
Manufacturer Part Number
GS880E32T-100
Description
512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS880E32T-100.pdf
(25 pages)
- Current page: 19 of 25
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Rev: 1.11 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipelined DCD Read Cycle Timing
DQ
B
A
ADSC
ADSP
A
–DQ
A
ADV
0
–B
GW
–A
BW
CK
E
E
E
D
G
D
n
1
2
3
Hi-Z
tS tH
tS tH
tS
tS
tS
RD1
Single Read
tH
tH
tH
tOLZ
tLZ
tS
tS
tS
tH
tKQ
tOE
E
2
tS tH
and E
RD2
Q1
tKH
A
tOHZ
3
19/25
only sampled with ADSP or ADSC
tKL
tKC
Burst Read
Q2
ADSP is blocked by E
tKQX
A
Suspend Burst
E
1
Q2
masks ADSP
B
GS880E18/32/36T-11/11.5/100/80/66
Q2c
ADSC initiated read
1
inactive
RD3
© 2000, Giga Semiconductor, Inc.
Q2
tH
tH
Deselected with E
D
Preliminary
Q3
A
tHZ
tKQX
2
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