GS88018T GSI [GSI Technology], GS88018T Datasheet - Page 7

• Manufacturer Part Number: GS88018T
• Description: 512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Notes:
1.
2.
3.
4.
Rev: 1.11 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
4th address
1st address
Write all bytes
Write all bytes
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
Write byte a
Write byte b
Write byte d
Write byte c
Function
Read
Read
C
Output Register Control
” and “
Power Down Control
Burst Order Control
Mode Name
D
” are only available on the x32 and x36 versions.
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
GW
H
H
H
H
H
H
H
L
A
, B
01
10
11
00
B
, B
C
and/or B
BW
10
11
00
01
H
L
L
L
L
L
L
X
D
Pin Name
may be used in any combination with BW to write single or multiple bytes.
11
00
01
10
LBO
FT
ZZ
B
H
H
H
H
X
X
L
L
A
7/25
H or NC
H or NC
L or NC
State
H
L
L
B
I
Note: The burst counter wraps to initial state on the 5th clock.
X
H
H
H
H
X
L
L
nterleaved Burst Sequence
B
2nd address
3rd address
4th address
1st address
B
X
H
H
H
H
X
L
L
C
Standby, I
GS88018/32/36T-11/11.5/100/80/66
Interleaved Burst
A[1:0] A[1:0] A[1:0] A[1:0]
Flow Through
Linear Burst
Function
00
01
10
11
Pipeline
Active
B
DD
X
H
H
H
H
X
L
L
D
= I
01
00
11
10
SB
© 2000, Giga Semiconductor, Inc.
Notes
2, 3, 4
2, 3, 4
2, 3, 4
10
11
00
01
2, 3
2, 3
1
1
Preliminary
11
10
01
00
BPR 1999.05.18