MT54W1MH36B-4 MICRON [Micron Technology], MT54W1MH36B-4 Datasheet - Page 3

• Manufacturer Part Number: MT54W1MH36B-4
• Manufacturer: MICRON [Micron Technology]

READ/WRITE OPERATIONS (continued)
edge. The address for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K that
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and to
provide fully coherent data for all combinations of
reads and writes. A read can immediately follow a
write, even if they are to the same address. Although
the write data has not been written to the memory
array, the SRAM will deliver the data from the write
register instead of using the older data from the mem-
ory array. The latest data is always utilized for all bus
transactions. WRITE cycles can be initiated on every K
rising edge.
PARTIAL WRITE OPERATIONS
the x8 devices in which nibble write is supported. The
active LOW byte write controls, BWx# (NWx#), are reg-
istered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
NOTE:
36Mb: 1.8V V
MT54W2MH18B_A.fm - Rev 9/02
MASTER
WRITE cycles are initiated by W# LOW at K rising
BYTE WRITE operations are supported, except for
In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets data setup and
hold times at the bus master.
ASIC)
(CPU
BUS
or
DD
, HSTL, QDRIIb2 SRAM
Delayed K#
DATA OUT
Delayed K
Source K#
DATA IN
Source K
Address
Write#
Read#
BW#
Vt
R
R
R = 50
D
SA
Vt = V
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
R
#
W
SRAM #1
#
REF
Application Example
W
B
#
/2
C C#
Figure 3
K
3
ZQ
K#
Q
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
resistor must be five times the desired impedance. For
example, a 350 W resistor is required for an output
impedance of 70 W . To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175 W to 350 W . Alternately, the ZQ ball
can be connected directly to V
the device in a minimum impedance mode.
because variations may occur over time in supply volt-
age and temperature. The device samples the value of
RQ. Impedance updates are transparent to the system;
they do not affect device operation, and all data sheet
timing and current specifications are met during an
update.
set at 50 W . To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
R = 250
The QDR SRAM is equipped with programmable
Output impedance updates may be required
The device will power up with an output impedance
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
, HSTL, QDRIIb2 SRAM
D
SA
R
Vt
Vt
R
#
W
SRAM #4
#
W
B
#
DD
Q, which will place
SS
C C#
. The value of the
©2002, Micron Technology Inc.
K
ADVANCE
ZQ
K#
Q
R = 250