MT54W1MH36B-4 MICRON [Micron Technology], MT54W1MH36B-4 Datasheet - Page 12

• Manufacturer Part Number: MT54W1MH36B-4
• Manufacturer: MICRON [Micron Technology]

TRUTH TABLE
Notes 1-6
BYTE WRITE OPERATION
Notes 7, 8
NOTE:
36Mb: 1.8V V
MT54W2MH18B_A.fm - Rev 9/02
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. ­ means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C and C# are
3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation, provided that
8. This table illustrates operation for the x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls
OPERATION
OPERATION
WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges
READ Cycle:
Load address, output data on
consecutive C and C# rising edges
NOP: No operation
STANDBY: Clock stopped
WRITE D0-17 at K rising edge
WRITE D0-17 at K# rising edge
WRITE D0-8 at K rising edge
WRITE D0-8 at K# rising edge
WRITE D9-17 at K rising edge
WRITE D9-17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
HIGH, then data outputs are delivered at K and K# rising edges.
transmission line charging symmetrically.
the setup and hold requirements are satisfied.
D18:D26) and BW3# (controls D27:D35). The x9 device operation is similar, except that BW1# and D8:D17 are not available. The x8
device operation is similar, except that NW0# controls D0:D3, and NW1# controls D4:D7.
DD
, HSTL, QDRIIb2 SRAM
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
Stopped
L®H
L®H
L®H
K
12
R#
X
H
X
L
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
W#
H
X
X
L
L®H
L®H
L®H
L®H
DD
K
, HSTL, QDRIIb2 SRAM
Q = High-Z
C#(t + 1)­
D
Q
Previous
D or Q
A
A
D = X
L®H
L®H
L®H
L®H
K(t)­
State
(A + 0)
(A + 0)
K#
at
at
BW0#
0
0
0
0
1
1
1
1
©2002, Micron Technology Inc.
Q = High-Z
Q
D
C(t + 2)­
Previous
ADVANCE
D or Q
A
A
K#(t)­
D = X
State
(A + 1)
(A + 1)
at
at
BW1#
0
0
1
1
0
0
1
1