MT16VDDF12864HG-202 MICRON [Micron Technology], MT16VDDF12864HG-202 Datasheet - Page 9

• Manufacturer Part Number: MT16VDDF12864HG-202
• Description: SMALL-OUTLINE DDR SDRAM DIMM
• Manufacturer: MICRON [Micron Technology]

Burst Length
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration. See Note 5 of Table 6, Burst Definition
Table, on page 10, for Ai values). The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. The programmed
burst length applies to both read and write bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram, on page 10.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Read and write accesses to the DDR SDRAM are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
9
operation or incompatibility with future versions may
result.
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Reserved states should not be used as unknown
0*
Figure 5: Mode Register Definition
14
BA1 BA0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
13
12
A12 A11
Operating Mode
M13
11
0
0
-
10
A10
M12 M11
0
0
-
9
A9
200-PIN DDR SODIMM
0
0
-
8
A8
M10
0
0
-
Diagram
7
A7 A6 A5 A4 A3
M9
M6
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
512MB, 1GB (x64)
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
M3
M6-M0
0
1
Valid
Valid
3
-
Burst Length
M2
0
0
0
0
1
1
1
1
2
CAS Latency
A2 A1 A0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
0
1
0
1
0
1
0
1
©2003 Micron Technology, Inc.
0
Interleaved
Burst Type
Sequential
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
2
4
8