MT16VDDF12864HG-202 MICRON [Micron Technology], MT16VDDF12864HG-202 Datasheet - Page 21

• Manufacturer Part Number: MT16VDDF12864HG-202
• Description: SMALL-OUTLINE DDR SDRAM DIMM
• Manufacturer: MICRON [Micron Technology]

09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
21. The refresh period 64ms. This equates to an aver-
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
ple of
value for
age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 8, Derating
Data Valid Window, shows derating curves for
duty cycles ranging between 50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
t
QH =
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
t
HP -
CK that meets the maximum absolute
t
RAS.
50/50
3.750
t
QHS). The data valid window derates
2.500
3.400
NA
49.5/50.5
3.700
-335
-262/-26A/-265 @ t CK = 10ns
-202 @ t CK = 10ns
-262/-26A/-265 @ t CK = 7.5ns
-202 @ t CK = 8ns
t
HP (
3.350
2.463
t
Figure 8: Derating Data Valid Window
CK/2),
49/51
3.650
2.425
3.300
t
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
3.250
t
48/52
3.550
QH
2.350
3.200
Clock Duty Cycle
21
47.5/53.5
3.500
25. To maintain a valid level, the transitioning edge of
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
2.313
3.150
the input must:
be ³ 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
47/53
3.450
must not vary more than 4 percent if CKE is
2.275
3.100
IH
IH
(AC).
(DC).
46.5/54.5
3.400
200-PIN DDR SODIMM
2.238
3.050
512MB, 1GB (x64)
3.350
46/54
2.200
3.000
45.5/55.5
3.300
2.163
2.950
©2003 Micron Technology, Inc.
3.250
45/55
2.900
2.125
t
DS and
IL
IL
(DC)
(AC)