K4H560438D-GC SAMSUNG [Samsung semiconductor], K4H560438D-GC Datasheet - Page 16

• Manufacturer Part Number: K4H560438D-GC
• Description: DDR 256Mb
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4H560838D
Overshoot/Undershoot specification
AC Operating Conditions
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
Notes 1. Includes ± 25mV margin for DC offset on V
DDR SDRAM IDD spec table
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
The area between the overshoot signal and VDD must be less than or equal to
The area between the undershoot signal and GND must be less than or equal to
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
IDD6
2. V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu
5. The value of V
3. V
lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
V
V
coupled TO V
TT
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
REF
ID
REF
Symbol
IDD4W
IDD2P
IDD2Q
IDD3P
IDD3N
IDD4R
IDD7A
is not applied directly to the device. V
IDD2F
is the magnitude of the difference between the input level on CK and the input level on CK.
IDD0
IDD1
IDD5
, and must track variations in the DC level of V
, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
Low power
Normal
Parameter/Condition
IX
REF
IX
is expected to equal 0.5*V
is expected to equal 0.5*V
, both of which may result in V
K4H560838D-GC(L)B3
Parameter
(DDR333)
120
170
170
180
325
1.5
90
25
20
35
55
3
3
TT
DDQ
DDQ
REF
is a system supply for signal termination resistors, is expected to be set equal to
of the transmitting device and must track variations in the DC level of the same.
, and a combined total of ± 50mV margin for all AC noise and DC offset on
of the transmitting device and must track variations in the dc level of the same.
REF
REF
noise. V
- 16 -
32Mx8
VIH(AC)
VID(AC)
VIX(AC)
Symbol
VIL(AC)
REF
should be de-coupled with an inductance of ≤ 3nH.
K4H560838D-GC(L)A2, B0
0.5*VDDQ-0.2
VREF + 0.31
(DDR266A/B)
Min
0.7
165
110
140
140
280
1.5
80
20
18
30
45
3
3
0.5*VDDQ+0.2
VREF - 0.31
VDDQ+0.6
Control pins
Address &
Max
4.5 V-ns
4.5 V-ns
Rev. 2.2 Mar. ’03
REF
1.6 V
1.6 V
and internal DRAM noise
Specification
(V
DDR SDRAM
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
=2.7V, T = 10
Unit
V
V
V
V
Data pins
2.5 V-ns
2.5 V-ns
Optional
1.2V
1.2V
Notes
Note
3
3
1
2
°C
)