K4H560438D-GC SAMSUNG [Samsung semiconductor], K4H560438D-GC Datasheet
K4H560438D-GC
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K4H560438D-GC Summary of contents
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... LDM,UDM/DM for write masking only • Auto & Self refresh • 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8 • 60 Ball FBGA package ORDERING INFORMATION Part No. K4H560438D-GC(L)B3 K4H560438D-GC(L)A2 K4H560438D-GC(L)B0 K4H560838D-GC(L)B3 K4H560838D-GC(L)A2 K4H560838D-GC(L)B0 K4H561638D-GC(L)B3 K4H561638D-GC(L)A2 K4H561638D-GC(L)B0 Operating Frequencies Speed @CL2 Speed @CL2 ...
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... DM is internally loaded to match DQ and DQS identically. ENCAPSULANT AREA 0.35 ± 0.05 π 0.45 1.10± 0.10 Organization Column Address 64Mx4 A0-A9, A11 32Mx8 16Mx16 Column address configuration - 2 - DDR SDRAM 8.00 ± 0.10 0. 6.40 0. 3.20 0. 1. 0.80 (0.90) (0.90) ± 0.05 (1.80) BOTTOM VIEW A0-A9 A0-A8 Rev. 2.2 Mar. ’03 ...
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... CSP DQ10 DQ8 VREF VDDQ VSSQ VSS CK DQ9 UDQS UDM CK DQ6 LDQS LDM WE VSSQ VDDQ VDD CAS DQ5 DQ7 DDR SDRAM A12 A11 A8 A6 CKE VSS RAS BA1 A0 A2 VDD CS BA0 A10 A12 ...
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... LRAS LCBR CK, CK CKE 4 CK, CK Data Input Register Serial to parallel 8 8Mx8 8Mx8 8Mx8 8Mx8 Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS DDR SDRAM DQi LWCBR CK, CK Rev. 2.2 Mar. ’03 Data Strobe ...
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... LRAS LCBR CK, CK CKE 8 CK, CK Data Input Register Serial to parallel 16 4Mx16 4Mx16 4Mx16 4Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS DDR SDRAM DQi LWCBR CK, CK Rev. 2.2 Mar. ’03 Data Strobe ...
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... CK, CK CKE 16 CK, CK Data Input Register Serial to parallel 32 2Mx32 2Mx32 2Mx32 2Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS DDR SDRAM LWE LDM 32 16 x16 DQi LWCBR CK, CK Rev. 2.2 Mar. ’03 Data Strobe ...
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... Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. No Connect : No internal electrical connection is present. DQ Power Supply : +2.5V ± 0.2V. DQ Ground. Power Supply : +2.5V ± 0.2V (device specific). Ground. SSTL_2 reference voltage DDR SDRAM Rev. 2.2 Mar. ’03 ...
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... DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) ...
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... Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H560438D is 268,435,456 bits of double data rate synchronous DRAM organized 16,777,216 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... V REF REF is a system supply for signal termination resistors, is expected to be set equal to TT REF of the transmitting device and must track variations in the dc level of the same. DDQ 64Mx4 K4H560438D-GC(L)B3 K4H560438D-GC(L)A2,B0 (DDR333) 90 110 150 160 ...
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... K4H560438D AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2 ...
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... K4H560438D Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time ...
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... K4H560438D 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) ± 280 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 ±0.25 ±0.5 This derating table is used to increase t is calated as 1/SlewRate1-1/SlewRate2 ...
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... K4H560438D AC Operating Test Conditions Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate (for imput only) Input slew rate (I/O pins) Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition ...
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... Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H560838D is 268,435,456 bits of double data rate synchronous DRAM organized 8,388,608 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... K4H560838D Notes 1. Includes ± 25mV margin for DC offset bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF coupled both of which may result in V REF not applied directly to the device and must track variations in the DC level of V REF 3 ...
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... DDR SDRAM A2 B0 (DDR266A) (DDR266B) Min Max Min Max 120K 45 120K 7 7.5 12 7.5 12 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 -0.75 +0.75 -0.75 +0.75 -0 ...
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... Input setup/hold slew rate IS IH ∆tDS ∆tDH (ps) (ps +75 +75 +150 +150 /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate DDR SDRAM A2 B0 (DDR266A) (DDR266B) Min Max Min Max 15 15 0.5 0.5 0.5 0.5 2.2 2.2 1.75 1 ...
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... DQ and DQS slew rates differ. The Delta Rise/Fall Rate DS DH ∆tDSS/tDSH ∆tAC/tDQSCK (ps) (ps) (ps +50 +50 +50 +100 +100 - 19 - ∆tLZ(min) ∆tHZ(max) (ps) (ps -50 +50 -100 +100 Rev. 2.2 Mar. ’03 DDR SDRAM ...
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... REF V tt See Load Circuit V =0.5*V tt DDQ R =50Ω T Z0=50Ω V REF =0.5*V DDQ C =30pF LOAD Output Load Circuit (SSTL_2) Symbol Min CIN1 1.5 CIN2 1.5 COUT 3.5 CIN3 3 DDR SDRAM Unit V DDQ V V/ns V/ns -0.31 V REF V V Max Delta Cap(max) 3.5 0.5 3.5 0.25 5.5 0.5 5.5 Rev. 2.2 Mar. ’03 Note Unit ...
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... Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H561638D is 268,435,456 bits of double data rate synchronous DRAM organized 4,194,304 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... K4H561638D Notes 1. Includes ± 25mV margin for DC offset bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF coupled both of which may result in V REF not applied directly to the device and must track variations in the DC level of V REF 3 ...
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... DDR SDRAM A2 B0 (DDR266A) (DDR266B) Min Max Min Max 120K 45 120K 7 7.5 12 7.5 12 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 -0.75 +0.75 -0.75 +0.75 -0 ...
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... Input setup/hold slew rate IS IH ∆tDS ∆tDH (ps) (ps +75 +75 +150 +150 /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate DDR SDRAM A2 B0 (DDR266A) (DDR266B) Min Max Min Max 15 15 0.5 0.5 0.5 0.5 2.2 2.2 1.75 1 ...
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... DQ and DQS slew rates differ. The Delta Rise/Fall Rate DS DH ∆tDSS/tDSH ∆tAC/tDQSCK (ps) (ps) (ps +50 +50 +50 +100 +100 - 25 - ∆tLZ(min) ∆tHZ(max) (ps) (ps -50 +50 -100 +100 Rev. 2.2 Mar. ’03 DDR SDRAM ...
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... REF V tt See Load Circuit V =0.5*V tt DDQ R =50Ω T Z0=50Ω V REF =0.5*V DDQ C =30pF LOAD Output Load Circuit (SSTL_2) Symbol Min CIN1 1.5 CIN2 1.5 COUT 3.5 CIN3 3 DDR SDRAM Unit V DDQ V V/ns V/ns -0.31 V REF V V Max Delta Cap(max) 3.5 0.5 3.5 0.25 5.5 0.5 5.5 Rev. 2.2 Mar. ’03 Note Unit ...