IC42S16800 ICSI [Integrated Circuit Solution Inc], IC42S16800 Datasheet - Page 27

• Manufacturer Part Number: IC42S16800
• Description: 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
PRECHARGE TERMINATION
PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
CAS latency =2
DQ
CAS latency =3
DQ
CLK
Command
command
T0
Read
Read
T1
RP
from the precharge command.
T2
Q0
T3
Q1
Q0
T4
PRE
PRE
Q2
Q1
T5
t
RP
Q2
Q3
T6
t
RP
ACT
Q3
Hi-Z
T7
Burst lengh= X
ACT
Hi-Z
T8
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