K4T51043QG SAMSUNG [Samsung semiconductor], K4T51043QG Datasheet - Page 4

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K4T51043QG

Manufacturer Part Number
K4T51043QG
Description
512Mb G-die DDR2 SDRAM Specification
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
K4T51043QG
Manufacturer:
SPANSION
Quantity:
20 000
K4T51043QG
K4T51083QG
K4T51163QG
1.0 Ordering Information
Note :
1. Speed bin is in order of CL-tRCD-tRP
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
2.0 Key Features
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
128Mx4
32Mx16
64Mx8
• JEDEC standard V
• V
• 200 MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
• Average Refresh Period 7.8us at lower than T
• All of products are Lead-Free, Halogen-Free, and RoHS com-
Org.
CAS Latency
tRCD(min)
pin, 333MHz f
sec/pin
strobe is an optional feature)
3.9us at 85°C < T
pliant
tRC(min)
tRP(min)
Speed
DDQ
SDRAM Device Operation & Timing Diagram”
-50ohm ODT
-High Temperature Self-Refresh rate enable
K4T51043QG-HC(L)E7 K4T51043QG-HC(L)F7
K4T51083QG-HC(L)E7 K4T51083QG-HC(L)F7
K4T51163QG-HC(L)E7 K4T51163QG-HC(L)F7
= 1.8V ± 0.1V
DDR2-800 5-5-5
CK
for 400Mb/sec/pin, 267MHz f
CK
DDR2-800 5-5-5
for 667Mb/sec/pin, 400MHz f
CASE
DD
12.5
12.5
57.5
= 1.8V ± 0.1V Power Supply
< 95 °C
5
DDR2-800 6-6-6
DDR2-800 6-6-6
CK
15
15
60
6
for 533Mb/sec/
CASE
CK
for 800Mb/
85°C,
K4T51043QG-HC(L)E6 K4T51043QG-HC(L)D5 K4T51043QG-HC(L)CC
K4T51083QG-HC(L)E6 K4T51083QG-HC(L)D5 K4T51083QG-HC(L)CC
K4T51163QG-HC(L)E6
DDR2-667 5-5-5
DDR2-667 5-5-5
4 of 47
15
15
60
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x
4banks or 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 512Mb(x8) device receive
14/10/2 addressing.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V V
The 512Mb DDR2 device is available in 60ball FBGAs(x8) and in
84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in
5
this data sheet are for the DLL Enabled mode of operation.
K4T51163QG-HC(L)D5 K4T51163QG-HC(L)CC
DDR2-533 4-4-4
DDR2-533 4-4-4
15
15
60
4
Rev. 1.4 December 2008
DDQ
DDR2-400 3-3-3
DDR2-400 3-3-3
.
DDR2 SDRAM
15
15
55
3
Package
60 FBGA
60 FBGA
84 FBGA
Units
tCK
ns
ns
ns

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