K4T1G044QM-ZCCC SAMSUNG [Samsung semiconductor], K4T1G044QM-ZCCC Datasheet - Page 9

• Manufacturer Part Number: K4T1G044QM-ZCCC
• Description: 1Gb M-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

1Gb M-die DDR2 SDRAM
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
(UDQS), (UDQS)
(RDQS), (RDQS)
(LDQS), (LDQS)
RAS, CAS, WE
2.2 Input/Output Functional Description
DQS, (DQS)
BA0 - BA2
V
V
A0 - A13
Symbol
CK, CK
DD
SS
V
V
V
CKE
ODT
DM
DQ
NC
SSDL
CS
DDL
REF
/V
/V
DDQ
SSQ
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
Input/Output
Input/Output
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Type
x16 LDQS and UDQS
x4 DQS/DQS
x8 DQS/DQS
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
x4 DQS
x8 DQS
x8 DQS, RDQS, if EMRS(1) [A11] = 1
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. After V
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, V
write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down.
Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
Rank selection on systems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM
signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, UDQS/UDQS,
LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register
Set(EMRS) is programmed to disable ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Pre-
charge command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provided the row address for Active commands and the column address and
Auto Precharge bit for Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-
charged, the bank is selected by BA0, BA1 and BA2. The address inputs also provide the op-code
during Mode Register Set commands.
Data Input/ Output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the
data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to
simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to
provide differential pair signaling to the system during both reads and writes. An EMRS(1) control
bit enables or disables all complementary data strobe signals.
No Connect: No internal electrical connection is present.
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Ground, DQ Ground
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
Reference voltage
REF
must be maintained to this input. CKE must be maintained high throughout read and
if EMRS(1) [A11] = 0
REF
Page 9 of 29
has become stable during the power on and initialization swquence, it
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
Function
Rev.1.1 Jan. 2005
DDR2 SDRAM