K4T1G044QM-ZCCC SAMSUNG [Samsung semiconductor], K4T1G044QM-ZCCC Datasheet - Page 12

• Manufacturer Part Number: K4T1G044QM-ZCCC
• Description: 1Gb M-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

1Gb M-die DDR2 SDRAM
Operating Temperature Condition
Input DC Logic Level
Input AC Logic Level
AC Input Test Conditions
Notes:
1.
2.
3.
V
V
SLEW
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required,
REF
SWING(MAX)
Symbol
V
V
Symbol
V
Symbol
V
please refer to JESD51.2 standard.
and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input waveform timing is referenced to the input signal crossing through the V
The input signal minimum slew rate is to be maintained over the range from V
from V
AC timings are referenced with input waveforms switching from V
V
IH
IL
IH
IL
IL
Symbol
TOPER
(DC)
(DC)
(AC)
(AC)
(AC) on the negative transitions.
REF
to V
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
IL
(AC) max for falling edges as shown in the below figure.
DC input logic high
AC input logic high
DC input logic low
AC input logic low
Parameter
Operating Temperature
Parameter
Parameter
V
Falling Slew =
SWING(MAX)
Condition
delta TF
V
REF
< AC Input Test Signal Waveform >
V
V
- V
delta TF
REF
REF
IL
(AC) max
- 0.3
Min.
Min.
+ 0.125
+ 0.250
-
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Rating
0 to 95
V
V
0.5 * V
1.0
1.0
V
REF
REF
IL
DDQ
delta TR
(AC) to V
Max.
Max.
Value
- 0.125
- 0.250
-
Rising Slew =
DDQ
+ 0.3
IH
IH/IL
REF
(AC) on the positive transitions and V
V
V
V/ns
(AC) level applied to the device under test.
to V
Units
°C
Units
Units
Units
V
IH
V
V
V
V
IH
(AC) min for rising edges and the range
(AC) min - V
V
V
V
V
V
V
V
delta TR
DDQ
IH
IH
REF
IL
IL
SS
(DC) max
(AC) max
(AC) min
(DC) min
1
1
2, 3
REF
Notes
1, 2, 3
Notes
Notes
Notes
Rev.1.1 Jan. 2005
DDR2 SDRAM
IH
(AC) to