M36L0T7050B2ZAQT NUMONYX [Numonyx B.V], M36L0T7050B2ZAQT Datasheet - Page 11

• Manufacturer Part Number: M36L0T7050B2ZAQT
• Description: 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
• Manufacturer: NUMONYX [Numonyx B.V]

M36L0T7050T2, M36L0T7050B2
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
PSRAM Chip Enable Input (E2
The Chip Enable, E2
This is the lowest power mode.
PSRAM Write Enable (W
The Write Enable, W
PSRAM Output Enable (G
The Output Enable, G
cycles to be achieved with the common I/O data bus.
PSRAM Upper Byte Enable (UB
The Upper Byte Enable, UB
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a Write or Read operation.
V
V
the main power supply for all Flash operations (Read, Program and Erase).
V
The V
driving the refresh logic, even when the device is not being accessed.
V
V
powered independently of the Flash Memory core power supply, V
DDF
DDQ
DDF
CCP
DDQ
provides the power supply to the internal cores of the Flash memory component. It is
CCP
provides the power supply for the Flash memory I/O pins. This allows all Outputs to be
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage supplies the power for all operations (Read or Write) and for
P
P
, puts the device in Deep Power-down mode when it is driven Low.
, controls the Bus Write operation of the memory.
P
, provides a high speed tri-state control, allowing fast read/write
P
P
, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
P
)
P
)
P
)
P
P
)
)
DDF
.
Signal descriptions
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