TH50VSF2581AASB TOSHIBA [Toshiba Semiconductor], TH50VSF2581AASB Datasheet - Page 29
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TH50VSF2581AASB
Manufacturer Part Number
TH50VSF2581AASB
Description
SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
Manufacturer
TOSHIBA [Toshiba Semiconductor]
Datasheet
1.TH50VSF2581AASB.pdf
(50 pages)
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HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY
during an auto mode operation. The output data is read out using the same timing as that used when CEF = OE
= V
Hardware Sequence flag is read to determine the device status and the result of the operation is verified by
comparing the read-out data with the original data.
The TH50VSF2580/2581AASB has a Hardware Sequence flag which allows the device status to be determined
The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The
IL
DQ7 (
function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation,
DQ7 outputs inverted data during the programming operation and outputs actual data after programming has
finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase
operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.
signal.
DQ6 (Toggle bit 1)
operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately
outputs a 0 or a 1 for each OE access while CEF = V
has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the
operation fails, the DQ6 output toggles.
3 µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block,
DQ6 will toggle for around 100 µs. It will then stop toggling. After toggling has stopped the device will return to
Read Mode.
DQ5 (internal time-out)
operation has not been completed within the allotted time.
outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read
Mode.
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling
When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE
The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase
If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around
If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the
Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5
in Read Mode. The
DATA
polling)
RY
/
BY
output can be either High or Low.
IL
while the device is busy. When the internal operation
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