TH50VSF2581AASB TOSHIBA [Toshiba Semiconductor], TH50VSF2581AASB Datasheet - Page 18

• Manufacturer Part Number: TH50VSF2581AASB
• Description: SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
• Manufacturer: TOSHIBA [Toshiba Semiconductor]

COMMAND WRITE/PROGRAM/ERASE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
CMD
AS
AH
AHW
DS
DH
WELH
WEHH
CES
CEH
CELH
CEHH
WES
WEH
OES
OEHP
OEHT
AST
AHT
BEH
VCS
BUSY
RP
READY
RB
RH
CEBTS
SUSP
RESP
SUSE
RESE
Command Write Cycle Time
Address Set-up Time / BYTE Set-up Time
Address Hold Time / BYTE Hold Time
Address Hold Time from WE High level
Data Set-up Time
Data Hold Time
Address Set-up Time (Toggle)
Address Hold Time (toggle)
Erase Hold Time
V
Program/Erase Valid to
Program Suspend Command to Suspend Mode
Program Resume Command to Program Mode
Erase Suspend Command to Suspend Mode
Erase Resume Command to Erase Mode
RESET Low-Level Hold Time
RESET Low-Level to Read Mode
RY
RESET Recovery Time
WE Low-Level Hold Time
WE High-Level Hold Time
CEF Set-up Time to WE Active ( WE Control)
CEF Hold Time from WE High Level
CEF Low-Level Hold Time
CEF High-Level Hold Time
WE Set-up time to CEF Active ( CEF Control)
WE Hold Time from CEF High Level
OE Set-up Time
OE Hold Time (Toggle, Data Polling)
OE High-Level Hold Time (Toggle)
CEF Set-up time BYTE Transition
CCf
/
BY
Set-up Time
Recovery Time
RY
/
BY
Delay
PARAMETER
( WE Control)
( WE Control)
( CEF Control)
( CEF Control)
( WE Control)
( CEF Control)
TH50VSF2580/2581AASB
MIN
120
500
500
50
20
50
50
20
50
20
90
20
50
50
2001-10-26 18/50






0
0
0
0
0
0
0
0
0
0
5
MAX
1.5



















90

20



15
1
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs