SCN68681E1F40 PHILIPS [NXP Semiconductors], SCN68681E1F40 Datasheet - Page 16

• Manufacturer Part Number: SCN68681E1F40
• Description: Dual asynchronous receiver/transmitter DUART
• Manufacturer: PHILIPS [NXP Semiconductors]

Duty cycle of 16x clock is 50%
Philips Semiconductors
1: The Channel A receiver interrupt output which is the complement
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00: The complement of OPR[3].
01: The counter/timer output, in which case OP3 acts as an open-
10: The 1X clock for the Channel B transmitter, which is the clock
11: The 1X clock for the Channel B receiver, which is the clock that
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00: The complement of OPR[2].
01: The 16X clock for the Channel A transmitter. This is the clock
10: The 1X clock for the Channel A transmitter, which is the clock
11: The 1X clock for the Channel A receiver, which is the clock that
Table 4.
NOTE:
1998 Sep 04
of ISR[1]. When in this mode OP4 acts as an open-drain output.
Dual asynchronous receiver/transmitter (DUART)
NORMAL RATE
Note that this output is not masked by the contents of the IMR.
drain output. In the timer mode, this output is a square wave at
the programmed frequency. In the counter mode, the output
remains High until terminal count is reached, at which time it
goes Low. The output returns to the High state when the count-
er is stopped by a stop counter command. Note that this output
is not masked by the contents of the IMR.
that shifts the transmitted data. If data is not being transmitted,
a free running 1X clock is output.
samples the received data. If data is not being received, a free
running 1X clock is output.
selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] = 1111.
that shifts the transmitted data. If data is not being transmitted,
a free running 1X clock is output.
samples the received data. If data is not being received, a free
running 1X clock is output.
(BAUD)
115.2K
14.4K
28.8K
57.6K
134.5
19.2k
38.4k
1050
1200
1800
2000
2400
4800
7200
9600
150
200
300
600
110
50
75
Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
CLOCK (kHz)
ACTUAL 16x
1843.2K
16.756
32.056
1.759
2.153
153.6
230.4
307.2
460.8
614.4
921.6
115.2
1%.
19.2
28.8
38.4
76.8
0.8
1.2
2.4
3.2
4.8
9.6
ERROR (%)
-0.069
-0.260
0.059
0.175
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a “clean” communications channel. The percent
of error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
due to a variable error of up to 1/16 bit time in receiver clock phase
alignment to the start bit.
Table 5.
NOTE:
*
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG:
Set 1: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k,
Set 2: 75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k,
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 4.
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 5.
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
000
001
010
011
100
101
110
111
ACR
[6:4]
In these modes, the Channel B receiver clock should normally be
generated from the baud rate generator. Timer mode generates
squarewave.
9.6k, and 38.4k baud.
9.6k, and 19.2k baud.
Counter
Counter
Counter
Counter
Timer (square wave)
Timer (square wave)
Timer (square wave)
Timer (square wave)
ACR 6:4 Field Definition
MODE
External (IP2)*
TxCA – 1x clock of Channel
A transmitter
TxCB – 1x clock of Channel
B transmitter
Crystal or external clock
(x1/CLK) divided by 16
External (IP2)*
External (IP2) divided by 16*
Crystal or external clock
(X1/CLK)
Crystal or external clock
(X1/CLK) divided by 16
CLOCK SOURCE
SCN68681
Product specification