IDT72V73273BB IDT, Integrated Device Technology Inc, IDT72V73273BB Datasheet - Page 3

• Manufacturer Part Number: IDT72V73273BB
• Description: IC DGTL SW 32768X32768 208-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V73273BB

• Circuit: 8 x 1:1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Independent Circuits: -
• Other names: 72V73273BB

PIN DESCRIPTION
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
A0-A15
BEL
C32i
CS
D0-15
DS
DTA/BEH
F32i
GND
ODE
RX0-63
RESET
R/W
S/A
TCK
TDI
TDO
TMS
TRST
SYMBOL
Address 0-15
Byte Enable LOW
Clock
Chip Select
Data Bus 0-15
Data Strobe
Data Transfer
Acknowledgment
Active LOW Output
/Byte Enable HIGH
Frame Pulse
Output Drive Enable
RX Input 0 to 63
Device Reset:
Read/Write
Synchronous/
Asynchronous
Bus Mode
Test Clock
Test Serial Data In
Test Serial Data Out
Test Mode Select
Test Reset
NAME
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
*See PQFP
Table Below
*See PQFP
Table Below
*See PQFP
Table Below
*See PQFP
Table Below
PIN NO.
PQFP
208
207
31
12
11
32
13
10
2
3
5
9
7
8
6
*See PBGA
*See PBGA
*See PBGA
Table Below
Table Below
Table Below
*See PBGA
Table Below
PIN NO.
PBGA
C1
A1
E1
D4
K2
B1
A2
E2
D2
C3
C2
D3
A3
D1
L4
3
These pins are the data bus of the microprocessor port.
These address lines access all internal memories.
In synchronous mode, this input will enable the lower byte (D0-7) on to the data
bus.
Serial clock for shifting data in/out on the serial data streams. This input accepts
a 32.768MHz clock.
Active LOW input used by a microprocessor to activate the microprocessor port
of the device.
This active LOW input works in conjunction with CS to enable the read and write
operations. This active LOW input sets the data bus lines (D0-D15).
In asynchronous mode this pin indicates that a data bus transfer is complete.
When the bus cycle ends, this pin drives HIGH and then High-Z allowing for
faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to
hold a HIGH level when the pin is High-Z. When the device is in
synchronous bus mode, this pin acts as an input and will enable the upper byte
(D8-15) on to the data bus.
This input accepts and automatically identifies frame synchronization signals
formatted according to ST-BUS and GCI specifications.
Ground.
This is the output enable control for the TX serial outputs. When ODE input is
LOW and the OSB bit of the CR register is LOW, all TX outputs are in a High-
Impedance state. If this input is HIGH, the TX output drivers are enabled.
However, each channel may still be put into a High-Impedance state by using
the per channel control bits in the Connection Memory HIGH.
Serial data Input Stream. These streams may have data rates of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s, 16.384Mb/s, or 32.768Mb/s depending upon the
selection in Receive Data Rate Selection Register (RDRSR).
This input (active LOW) puts the device in its reset state that clears the device
internal counters, registers and brings TX0-63 and microport data outputs to a
High-Impedance state. The RESET pin must be held LOW for a minimum of
20ns to reset the device.
This input controls the direction of the data bus lines (D0-D15) during a
microprocessor access.
This input will select between asynchronous microprocessor bus timing and
synchronous microprocessor bus timing. In synchronous mode, DTA/BEH
acts as the BEH input and is used in conjunction with BEL to output data on the
data bus. In asynchronous bus mode, BEL is tied LOW and DTA/BEH acts as
the DTA, data bus acknowledgment output.
Provides the clock to the JTAG test logic.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled
HIGH by an internal pull-up when not driven.
in High-Impedance state when JTAG scan is not enabled.
JTAG signal that controls the state transitions of the TAP controller. This pin is
pulled HIGH by an internal pull-up when not driven.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-
Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This
pin should be pulsed LOW on power-up, or held LOW, to ensure that the device
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held i
DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE