IDT72V90823BC IDT, Integrated Device Technology Inc, IDT72V90823BC Datasheet - Page 8

• Manufacturer Part Number: IDT72V90823BC
• Description: IC DGTL SW 2048X2048 100-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V90823BC

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V90823BC

CONSTANT DELAY MODE (V/C BIT = 1)
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V90823, the minimum throughput delay achievable in the constant
delay mode will be one frame. For example, in 2 Mb/s mode, when input time-
slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots of
delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame.
See Table 3.
MICROPROCESSOR INTERFACE
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to
determine what mode the IDT72V90823 should operate in.
timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode
2 multiplexed bus timing is selected.
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR),
Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and
Figure 13 for multiplexed parallel microport timing.
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed
microport timing.
connection and data memories. All locations provide read/write access except
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
registers and memories of the IDT72V90823.
interface mode selection (IMS), control (CR), frame alignment (FAR) and frame
input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are
used to select 32, 64, or 128 locations corresponding to data rate of the ST-
BUS
register allow access to the entire data and connection memories. The control
and IMS registers together control all the major functions of the device, see
Figure 3.
tions sections, after system power-up, the IMS register should be programmed
immediately to establish the desired switching configuration.
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
In this mode, frame integrity is maintained in all switching configurations by
The IDT72V90823 provides a parallel microprocessor interface for multi-
If the IM pin is low a Motorola non-multiplexed bus should be connected to
If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
For multiplexed operation, the required signals are the 8-bit data and
For the Motorola non-multiplexed bus, the required signals are the 16-bit
The IDT72V90823 microport provides access to the internal registers,
The address bus on the microprocessor interface selects the internal
If the A7 address input is low, then A6 through A0 are used to address the
As explained in the Serial Data Interface Timing and Switching Configura-
The data in the control register consists of the memory block programming
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. The address input lines and the stream address bits (STA) of the control
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entire connection memory block to be programmed. The memory select bit is
used to designate the connection memory or the data Memory. The stream
address bits select internal memory subsections corresponding to input or output
serial streams.
BPD4), block programming enable bit (BPE), output stand by bit (OSB), start
frame evaluation bit (SFE) and data rate selection bits (DR0-1). The block
programming and the block programming enable bits allows users to program
the entire connection memory (see Memory Block Programming section). If the
ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS
output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and
all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
1,024 or 2,048 bits, respectively. The contents of the CCO bit of each connection
memory location are output on the CCO pin once every frame. The contents
of the CCO bits of the connection memory are transmitted sequentially on to the
CCO pin and are synchronous with the data rates on the other serial streams.
the serial streams. For example, in 2.048 Mb/s mode (32 channels per frame),
the contents of the CCO bit in position 0 (TX0, CH0) of the connection memory
is output on the first clock cycle of channel 31 through CCO pin. The contents
of the CCO bit in position 32 (TX1, CH0) of the connection memory is output on
the second clock cycle of channel 31 via CCO pin.
location controls the output drivers-enables (if high) or disables (if low). See
Table 5 for detail.
Processor Mode and Connection Mode. If high, the contents of the connection
memory are output on the TX streams. If low, the stream address bit (SAB) and
the channel address bit (CAB) of the connection memory defines the source
information (stream and channel) of the time-slot that will be switched to the output
from data memory.
allows the per-channel selection between variable and constant throughput
delay modes.
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V90823
the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
The data in the IMS register consists of block programming bits (BPD0-
The CCO pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512,
The CCO bit is output one channel before the corresponding channel on
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
The processor channel (PC) bit of the connection memory selects between
The V/C (Variable/Constant Delay) bit in each connection memory location
If the LPBK bit is high, the associated TX output channel data is internally
After power up, the state of the connection memory is unknown. As such,
COMMERCIAL TEMPERATURE RANGE
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