SX1210 SEMTECH [Semtech Corporation], SX1210 Datasheet - Page 32

• Manufacturer Part Number: SX1210
• Description: Ultra-Low Power Integrated UHF Receiver
• Manufacturer: SEMTECH [Semtech Corporation]

In Buffered and Packet modes of operation, data that have been received are stored in a configurable FIFO (First
In First Out) device. It is accessed via the SPI Data interface and provides several interrupts for transfer
management.
The FIFO is 1 byte (8 bits) wide hence it only performs byte (parallel) operations, whereas the demodulator
functions serially. A shift register is therefore employed to interface the two devices. In Rx the shift register gets bit
by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.
The FIFO width is programmable, to 16, 32, 48 or 64 bytes via MCParam_Fifo_size
All interrupt sources and flags are configured in the IRQParam section of the configuration register, with the
exception of Fifo_threshold :
Rev 2– Sept 8
ADVANCED COMMUNICATIONS & SENSING
/Fifoempty: /Fifoempty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note
that when retrieving data from the FIFO, /Fifoempty is updated on NSS_DATA falling edge, i.e. when
/Fifoempty is updated to low state the currently started read operation must be completed. In other words,
/Fifoempty state must be checked after each read operation for a decision on the next one (/Fifoempty = 1:
more byte(s) to read; /Fifoempty = 0: no more byte to read).
Write_byte: Write_byte interrupt source goes high for 1 bit period each time a new byte is transferred from the
SR to the FIFO (i.e. each time a new byte is received)
Fifofull: Fifofull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
Fifo_overrun_clr: Fifo_overrun_clr flag is set when a new byte is written by the SR while the FIFO is already
full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared.
Fifo_threshold: Fifo_threshold interrupt source’s behavior can be programmed via MCParam_Fifo_thresh (B
value). This behavior is illustrated in Figure 25.
th
, 2008
5.2.2.2. Size Selection
5.2.2.3. Interrupt Sources and Flags
Data Rx
Figure 24: FIFO and Shift Register (SR)
1
MSB
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SR (8bits)
byte0
byte1
8
LSB
FIFO
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