SX1210 SEMTECH [Semtech Corporation], SX1210 Datasheet - Page 26
![no-image](/images/no-image-200.jpg)
SX1210
Manufacturer Part Number
SX1210
Description
Ultra-Low Power Integrated UHF Receiver
Manufacturer
SEMTECH [Semtech Corporation]
Datasheet
1.SX1210.pdf
(73 pages)
- Current page: 26 of 73
- Download datasheet (2Mb)
For proper operation, the Bit Synchronizer must first receive three bytes of alternating logic value preamble, i.e.
“0101” sequences. After this startup phase, the rising edge of DCLK signal is centered on the demodulated bit.
Subsequent data transitions will preserve this centering.
This has two implications:
This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily
achievable (crystal tolerance is in the range of 50 to 100 ppm).
Bit Synchronizer and Active channel filter settings are a function of the reference oscillator crystal frequency, F
Settings other than those programmable with a 12.8 MHz crystal can be obtained by selection of the correct
reference oscillator frequency. Please contact your local Semtech representative for further details.
After OOK or FSK demodulation, the baseband signal is made available to the user on pin 20, DATA, when
Continuous mode is selected.
In Buffered and Packet modes, the data is retrieved from the FIFO through the SPI interface.
Rev 2– Sept 8
ADVANCED COMMUNICATIONS & SENSING
Firstly, if the Bit Rates of Transmitter and Receiver are known to be the same, the SX1210 will be able to
receive an infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction.
If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the
BitSync can withstand can be estimated as:
3.3.12. Alternative Settings
3.3.13. Data Output
th
, 2008
NumberOfBi
Page 26 of 73
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SX1210
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