TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 33

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

June 2003
Agere Systems Inc.
Registers
Register Map
Table 6. Register Map
* ADDR values delimited by a comma indicate the address for each of two channels, from channel 1 or 2. For example, the register for Tx
† Reserved.
ADDR
[6:0]
control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control
signals are at address 38.
0A
0B
0C
0D
0E
00
01
02
03
04
05
06
08
09
0F
10
11
12
13
*
ISREG
IEREG
IAREG
IEREG
CREG
CREG
CREG
CREG
CREG
CREG
CREG
CREG
CREG
CREG
CREG
SREG
SREG
SREG
PREG
Type
Reg.
DB7
(continued)
—
—
—
—
—
—
—
—
—
—
†
†
†
†
†
†
†
†
†
†
DESCREAMBLER
SCRAMBLER/
CONTROL
DB6
—
—
—
—
—
—
—
—
—
†
†
†
†
†
†
†
†
†
PARALLEL
CONTROL
PARITY
DB5
BUS
—
—
—
—
—
—
—
—
—
I/O
†
†
†
†
†
†
†
†
†
TRANSMITTER B1 ERROR INSERT MASK
PER DEVICE
LINE LPBK
A1 ERROR INSERT VALUE
A2 ERROR INSERT VALUE
CONTROL
CONTROL
ENABLE
Rx TOH
Rx TOH
FRAME
CLOCK
DB4
AND
HI-Z
—
—
INT
—
—
Device Register Block
LOCKREG MSB
SCRATCH PAD
LOCKREG LSB
†
†
†
†
FIXED ID MSB
FIXED ID LSB
FIXED REV
FIFO ALIGNER THRESHOLD VALUE (max)
FIFO ALIGNER THRESHOLD VALUE (min)
EXT PROT
SW EN
DB3
NUMBER OF CONSECUTIVE A1/A2 ERRORS TO
—
—
—
—
—
ENABLE/MASK REGISTER [4:0]
†
†
†
†
†
TTSV02622 STS-24 Backplane Transceiver
EXT PROT
PARALLEL
SW FUNC
FOR CH1
OUTPUT
SELECT
PORT
DB2
MUX
—
—
—
—
GENERATE [3:0]
†
†
†
†
ERROR FLAG
ALIGNMENT
ENABLE/MASK REGISTER
COMMAND
REGISTER
WRITE TO
CH 2 INT
LOCKED
SELECT
STS-12
DB1
FIFO
—
†
LVDS LPBK
COMMAND
CONTROL
FOR CH1
CH 1 INT
OUTPUT
GLOBAL
SELECT
OFFSET
SERIAL
ERROR
FRAME
RESET
PORT
FLAG
DB0
MUX
Reset
Value
(hex)
NA
A0
01
01
00
00
00
00
0F
02
15
60
00
00
00
00
00
00
00
register block
register block
Comments
interrupts.
Top-level
Generic
register
Device
Device
block.
(Rx).
(Tx).
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