TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 32

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

TTSV02622 STS-24 Backplane Transceiver
Registers
Definition of Register Types
The TTSV02622 design contains six structural register elements: SREG, CREG, PREG, IAREG, ISREG, and
IEREG. There are no mixed registers in TTSV02622. This means that all bits of a particular register (particular
address) are structurally the same and are as follows:
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Status register (SREG):
— A status register is read only, and as the name implies is used to convey the status information of a particular
Control register (CREG):
— A control register is read and writable memory element inside CORE_CONTROL. The value of a CREG will
Pulse register (PREG):
— Each element, or bit, of a pulse register is a control or event signal that is asserted and then deasserted when
Interrupt alarm register (IAREG):
— Each bit of an interrupt alarm register is a event latch. When a particular event is produced in the TTSV02622
Interrupt status register (ISREG):
— Each bit of an interrupt status register is physically the logical OR function. It is a consolidation of lower-level
Interrupt enable register (IEREG):
— Each bit of a status register or alarm register has an associated enable bit. If this bit is set to value 1, then the
element or function of the TTSV02622 chip. The reset value of an SREG is really the reset value of the partic-
ular element or function that is being read. In some cases, an SREG is really a fixed value; an example of
which is the fixed id and revision registers.
always be the value written to it. Events inside the TTSV02622 chip cannot affect a CREG value. The only
exception is a soft reset, in which case the CREG will return to its reset value. The control register have reset
values as defined in the reset value column of Table 6 on page 33.
a value of 1 is written to it. This means that each bit is always of value 0 until it is written to, upon which it is
pulsed to the value of 1 and then returned to a value of 0. A pulse register will always have a read value of 0.
chip, its occurrence is latched by its associated IAREG bit. To clear a particular IAREG bit, a value of 1 must
be written to it. In the TTSV02622 chip, all IAREG reset values are 0.
interrupt alarms and/or ISREG bits from other registers. A direct result of the fact that each bit of the ISREG is
a logical OR function means that it will have a read value of 1 if any of the consolidation signals are of value 1,
and will be of value 0 if and only if all consolidation signals are of value 0. In the TTSV02622 chip, all ISREG
reset values are 0.
event is allowed to propagate to the next higher level of consolidation. If this bit is set to zero, then the associ-
ated IAREG or ISREG bit can still be asserted but an alarm will not propagate to the next higher level. Obvi-
ously, an interrupt enable bit is an interrupt mask bit when it is set to value 0.
Agere Systems Inc.
June 2003