TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 20

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

TTSV02622 STS-24 Backplane Transceiver
Supervisory Features
Note: On parallel output ports, parity is calculated over the 8-bit data bus and not on the SPE and C1J1 lines.
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Parallel bus integrity:
— Parity error checking is implemented on each of the four parallel input buses. Even and odd parity is sup-
TOH serial port integrity:
— There is even parity generation on each of the four TOH serial output ports. There is even parity error check-
LVDS link integrity:
— There is B1 parity generation on each of the four LVDS output channels. There is also performance monitoring
Framer monitor:
— The framer in the receive direction will report loss of frame (LOF) as an interrupt, as well as a LOF count and
Receiver internal path integrity:
— There is even parity generation in the receiver section (after descrambler). There is also even parity error
Pointer mover performance monitoring:
— There is pointer mover performance monitoring in the receiver section. Alarm indication signal path (AIS-P)
AIS-P is implemented as a per STS-1 interrupt. In case of concatenated payload, only the interrupt associated
with the head of the group will be active.
Concatenation is reported as a per STS-1 status, and is high when STS-1 is concatenated; and low when not
concatenated.
Elastic store overflow will generate an interrupt on a per STS-1 basis.
FIFO aligner monitoring:
— There is monitoring of the FIFO aligner operating point, and upon deviating from the nominal operating point
Frame offset monitoring:
— There is monitoring of the frame offset between all enabled channels (disabled channels must not interfere
CPU interface monitoring:
— There is monitoring of potential write cycles that may occur when operating in write protect mode. Upon
ported as controlled from the CPU interface (per device control). Upon detection of an error, an interrupt is
raised. This feature is on a per-channel basis.
ing on each of the four TOH serial input ports. There is one parity bit imbedded in the TOH frame. It occupies
the most significant bit location of A1 byte of STS-1. Upon detection of an error, an interrupt is raised. This fea-
ture is on a per-channel basis.
on each of the four LVDS input channels, implemented as B1 parity error checking. Upon detection of an error,
a counter is incremented (one count per errored bit) and an interrupt is raised. The counter is 7 bits wide plus
one overflow indicator bit. This feature is on a per-channel basis.
errored frame count. The LOF interrupt must not be clearable as long as the channel is in the LOF state. In
addition, the errored frame count must represent errored frames, and should not increment more than once
per frame even if there are multiple errors.
checking in the receiver section (before output). Upon detection of an error, an interrupt is raised. This feature
is on a per-channel basis.
and concatenation is reported, as well as elastic store overflows.
of the FIFO by more than user-programmable threshold values (min and max threshold values), an interrupt is
raised. Threshold values are defined per device, flags are per channel.
with the monitoring). Monitoring is performed continuously. Upon exceeding the maximum allowed frame off-
set (18 bytes) between all enabled channels, an interrupt is raised.
detecting a write access to the application specific integrated circuit (ASIC) when the device is in write protect
mode, an interrupt is raised (W-LOCK flag).
Agere Systems Inc.
June 2003