TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 14

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

TTSV02622 STS-24 Backplane Transceiver
Pin Information
Table 3. Pin Descriptions (continued)
14
Pin
M1
M2
M3
M4
C3
U1
U2
Y9
K1
A5
B6
K2
K3
A2
A3
A4
B1
B2
B3
B4
T1
T2
V1
T3
T4
(continued)
LVDS_RESH
LVDS_RESL
TSTSHFTLD
PLL_VDDA
PLL_VSSA
TSTMODE
RESETRN
RESETTN
LVDS_EN
PLL_REF
SCANEN
MRESET
BYPASS
TSTCLK
Symbol
TSTMD
TRSTN
REF10
REF14
HIZ_N
TCLK
DXP
DXN
TMS
TDO
TDI
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCHMITT
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-up/
Pull-Up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
I/O
—
—
—
—
—
—
—
O
I/
I/
I/
I/
I/
I/
I/
I/
I/
I/
I/
I/
I/
I/
I/
I
I
Global 3-state control.
Reference for PLL (10 k to GND).
1.0 V reference for LVDS reference block. See
1.4 V reference for LVDS reference block. See
Resistance high input (use 100
Resistance low input (use 100
Temperature-sensing diode (anode +).
Temperature-sensing diode (cathode –).
PLL analog V
PLL analog V
JTAG clock input.
JTAG data input.
JTAG mode select input.
JTAG data output.
JTAG reset input.
Scan test mode input.
Scan mode enable input.
LVDS enable used during boundary scan (B-S).
Enables CDR test mode.
Enables bypassing of the 622 MHz clock synthesis
Test clock for emulation of 622 MHz clock during PLL
Test mode reset.
Resets receiver clock division counter.
Resets transmitter clock division counter.
Enables the test mode control register for shifting-in
Figure 3 on page 16.
Figure 3 on page 16.
input).
input).
with TSTCLK.
bypass.
selected tests by a serial port.
DD
SS
(GND).
(3.3 V).
Description
to LVDS_RESH
to LVDS_RESL
Agere Systems Inc.
June 2003