9DB1233AGLF IDT [Integrated Device Technology], 9DB1233AGLF Datasheet - Page 5

• Manufacturer Part Number: 9DB1233AGLF
• Description: Twelve Output Differential Buffer for PCIe Gen3
• Manufacturer: IDT [Integrated Device Technology]

IDT
1
2
TA = T
1
2
3
4
5
Electrical Characteristics - Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Parameters
SMBus Output Low Voltage
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are >200 mV
DIF_IN input
The differential input clock must be running for the SMBus to be active
3.3V Logic Supply Voltage
Guaranteed by design and characterization, not 100% tested in production.
SMBus Input High Voltage
3.3V Core Supply Voltage
SMBus Input Low Voltage
Operation under these conditions is neither implied nor guaranteed.
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
®
Junction Temperature
Storage Temperature
Input ESD protection
Nominal Bus Voltage
SMBus Sink Current
Input SS Modulation
Ambient Operating
Input High Voltage
Input High Voltage
Input High Voltage
Twelve Output Differential Buffer for PCIe Gen3
Input Low Voltage
Input Low Voltage
SMBus Operating
Input Frequency
Clk Stabilization
Pin Inductance
PARAMETER
COM;
PARAMETER
Input Current
OE# Latency
Temperature
Capacitance
Tdrive_PD#
Frequency
Frequency
Trise
Supply Voltage VDD = 3.3 V +/-5%
Tfall
SYMBOL
SYMBOL
ESD prot
C
f
t
V
V
V
I
t
V
f
MAXSMB
V
T
LATOE#
VDDA
INDIF_IN
PULLUP
t
T
C
DRVPD
t
F
MODIN
VDD
OLSMB
DDSMB
RSMB
V
I
F
L
C
IHSMB
FSMB
V
ILSMB
STAB
IHSMB
I
V
V
COM
INP
t
Ts
ibyp
OUT
t
Tj
IN
pin
ipll
R
IH
IN
F
IL
IL
IH
V
stabilization or de-assertion of PD# to 1st clock
IN
V
Single-ended inputs, V
IN
= VDD; Inputs with internal pull-down resistors
From V
Single-ended inputs, except SMBus, low
Single-ended inputs, except SMBus, low
= 0 V; Inputs with internal pull-up resistors
Maximum SMBus operating frequency
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
V
DIF stop after OE# deassertion
DIF_IN differential clock inputs
DD
DIF start after OE# assertion
threshold and tri-level inputs
threshold and tri-level inputs
Logic Inputs, except DIF_IN
V
Except for SMBus interface
Rise time of control inputs
SMBus clock and data pins
DD
Fall time of control inputs
= 3.3 V, 100MHz PLL mode
DD
Output pin capacitance
(Triangular Modulation)
DIF output enable after
Allowable Frequency
Power-Up and after input clock
Commmercial range
Single-ended inputs
= 3.3 V, Bypass mode
Human Body Model
3V to 5V +/- 10%
PD# de-assertion
CONDITIONS
CONDITIONS
@ I
@ V
PULLUP
IN
OL
= GND, V
5
IN
= VDD
GND - 0.3
GND-0.5
MIN
-200
1.5
1.5
2.1
2.7
10
90
30
2000
-5
MIN
0
2
4
4
-65
100.00
TYP
TYP
V
V
V
DD
MAX
1000
200
166
110
300
DDSMB
DD
300
100
0.8
1.8
0.8
0.4
5.5
70
33
12
MAX
5.5V
5
7
5
5
6
5
5
+ 0.3
150
125
4.6
4.6
+0.5V
UNITS NOTES
cycles
MHz
MHz
kHz
kHz
UNITS NOTES
ms
mA
uA
uA
nH
pF
pF
pF
us
ns
ns
° C
ns
ns
V
V
V
V
V
V
°
° C
V
V
V
V
V
V
C
1675B—11/08/10
1,4
1,2
1,3
1,3
1,2
1,2
1,5
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1
1
1
1
1
1